View M7040N-083ZA1T_1742952.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/159 preliminary data may 2002 m7040n 64k x 72-bit entry network packet search engine features summary 64k data entries in 72-bit mode table may be partitioned into up to eight (8) octants (data entry width in each octant is configurable as 36, 72, 144, or 288 bits.) up to 100 million sustained searches per second in 72-bit and 144-bit configurations up to 50 million searches per second in 36-bit and 288-bit configurations searches any sub-field in a single cycle offers bit-by-bit and global masking synchronous, pipelined operation up to 31 search engines cascadable without performance degradation when cascaded, the database entries can scale from 496k to 3968k depending on the width of the entry glueless interface to industry- standard srams simple hardware instruction interface ieee 1149.1 test access port operating supply voltages include: v dd (operating core supply voltage) = 1.5v for 66 and 83msps; 1.65v for 100msps v ddq (operating supply voltage for i/o) = 2.5 or 3.3v 388 pbga, 35mm x 35mm figure 1. 388-ball pbga package 388-ball pbga 35mm x 35mm
m7040n 2/159 table of contents description ....................................................................7 overview......................................................................7 performance ...................................................................7 applications....................................................................7 product range (table 1.) . ........................................................7 switch/router implementation using the m7040n (figure 2.) .............................7 signalnames(table2.)..........................................................8 connections (figure 3.) . . . ........................................................9 m7040nblockdiagram(figure4.).................................................10 maximumrating................................................................11 absolutemaximumratings(table3.) ..............................................11 dc and ac parameters. . .......................................................12 dc and ac measurement conditions (table 4.) . . . ....................................12 m7040n 1.8, 2.5, or 3.3v ac testing load (figure 5.) ..................................13 m7040n 1.8, 2.5, or 3.3v input waveform (figure 6.) ..................................13 m7040n1.8,2.5,or3.3vi/ooutputloadequivalent(figure7.) .........................13 capacitance (table 5.) . . . .......................................................14 dccharacteristics(table6.) .....................................................14 actimingwaveformswithclk2x(figure8.)........................................15 actimingwaveformswithclk1x(figure9.)........................................16 actimingparameterswithclk2x(table7.) ........................................17 actimingparameterswithclk1x(table8.) ........................................18 operation.....................................................................19 commandbusanddqbus ......................................................19 databaseentry(dataarrayandmaskarray).........................................19 arbitration logic. . . .............................................................19 pipelineandsramcontrol.......................................................19 fulllogic.....................................................................19 connection descriptions . . .......................................................19 clocks ........................................................................21 clocks(clk2xandphs_l)(figure10.) ............................................21 clocks(clk1x)(figure11.)......................................................21 clocksforalltimingdiagrams(figure12.) ..........................................22 pllusage .....................................................................22
3/159 m7040n registers .....................................................................22 registeroverview(table9.)......................................................22 comparandregisters...........................................................23 comparandregisterselectionduringsearchandlearninstructions(figure13.).........23 maskregisters................................................................23 addressingtheglobalmasksregisterarray(figure14.) ...............................23 search-successful registers (ssr[0:7]) . ..........................................24 search-successful register (ssr) description (table 10.) .............................24 thecommandregister .........................................................25 commandregisterfielddescriptions(table11.).....................................25 theinformationregister.........................................................26 informationregisterfielddescriptions(table12.) ....................................26 thereadburstaddressregister(rburreg).......................................27 readburstregisterdescription(table13.)..........................................27 the write burst address register (wburreg). . . ....................................27 writeburstregisterdescription(table14.)..........................................27 thenfaregister..............................................................27 nfaregister(table15.).........................................................27 search engine architecture . .................................................28 dataandmaskaddressing.......................................................28 m7040ndatabasewidthconfiguration(figure15.) ...................................28 bitpositionmatch(table16.).....................................................29 multi-widthconfigurationexample(figure16.) .......................................29 m7040ndataandmaskarrayaddressing(figure17.).................................29 command codes and parameters ..............................................30 commandcodes...............................................................30 commandsandcommandparameters .............................................30 commandcodes(table17.) .....................................................30 commandparameters(table18.) .................................................31 readcommand.................................................................32 singlelocationreadcycletiming(figure18.)......................................33 burstreadofthedataandmaskarrays(blen=4)(figure19.) ........................33 readcommandparameters(table19.)............................................34 dataandmaskarray,sramreadaddressformat(table20.) ..........................34 readaddressformatforinternalregisters(table21.)................................35 readaddressformatfordataandmaskarrays(table22.) ............................35
m7040n 4/159 writecommand................................................................35 singlelocationwritecycletiming(figure20.) .....................................36 burstwriteofthedataandmaskarrays(blen=4)(figure21.)........................37 (single)writeaddressformatfordataandmaskarraysorsram(table23.).............37 writeaddressformatforinternalregisters(table24.)...............................38 writeaddressformatfordataandmaskarray(burstwrite)(table25.)..................38 parallelwrite ................................................................38 search command . .............................................................38 72-bitconfigurationwithsingledevice...........................................38 hardwarediagramforatablewithonedevice(figure22.).............................39 72-bitconfigurationsearchtimingdiagramforonedevice(figure23.).................40 x72tablewithonedevice(figure24.) .............................................41 latencyofsearchfrominstructiontosramaccesscycle,72-bit(table26.)..............41 shiftofssfandssvfromsadr(table27.).........................................41 72-bit search on tables configured as x72 using up to eight m7040n devices .........42 hit/missassumption(table28.)...................................................43 hardwarediagramforatablewitheightdevices(figure25.) ...........................43 x72tablewitheightdevices(figure26.)............................................44 timing diagrams for x72 using up to eight m7040n devices .............................45 latencyofsearchfrominstructiontosramaccesscycle(table29.) ...................48 shiftofssfandssvfromsadr(table30.).........................................48 72-bit search on tables configured as x72 using up to 31 m7040n devices . . ..........48 hit/missassumption(table31.)...................................................49 hardwarediagramforatablewith31devices(figure30.) .............................50 hardwarediagramforablockofuptoeightdevices(figure31.)........................51 x72tablewith31devices(figure32.)..............................................52 timingdiagramsforx72usingupto31m7040ndevices..............................53 latencyofsearchfrominstructiontosramaccesscycle(table32.) ...................64 shiftofssfandssvfromsadr(table33.).........................................64 144-bitconfigurationwithsingledevice ..........................................64 hardwarediagramforatablewith1device(figure44.) ...............................65 timing diagram for a 144-bit search for 1 device (figure 45.) . . . .......................66 x144tablewithonedevice(figure46.) ............................................67 latencyofsearchfrominstructiontosramaccesscycle,144-bit(table34.).............67 shiftofssfandssvfromsadr(table35.).........................................67 144-bitsearchontablesconfiguredasx144usinguptoeightm7040ndevices........68 hit/missassumption(table36.)...................................................69 hardwarediagramforatablewitheightdevices(figure47.) ...........................69 x144tablewitheightdevices(figure48.)...........................................70 timingdiagramsforx144usinguptoeightm7040ndevices ...........................71 latencyofsearchfrominstructiontosramaccesscycle,144-bit(table37.).............74 shiftofssfandssvfromsadr(table38.).........................................74
5/159 m7040n 144-bitsearchontablesconfiguredasx144usingupto31m7040ndevices...........74 hit/missassumption(table39.)...................................................75 hardwarediagramforatablewith31devices(figure52.) .............................76 hardwarediagramforablockofuptoeightdevices(figure53.) ........................77 x144tablewith31devices(figure54.).............................................78 timing diagrams for x144 using up to 31 m7040n devices .............................79 latencyofsearchfrominstructiontosramaccesscycle,144-bit(table40.).............90 shiftofssfandssvfromsadr(table41.).........................................90 288-bit search on tables configured as x288 using a single m7040n device ..........90 hardwarediagramforatablewithonedevice(figure66.).............................91 timingdiagramfor288-bitsearch(onedevice)(figure67.) ..........................92 x288tablewithonedevice(figure68.) ............................................93 latencyofsearchfromcyclescanddtosramaccesscycle(table42.)...............93 shiftofssfandssvfromsadr(table43.).........................................93 288-bit search on tables x288-configured using up to eight m7040n devices .........94 hit/missassumption(table44.)...................................................95 hardwarediagramforatablewitheightdevices(figure69.) ...........................96 x288tablewitheightdevices(figure70.)...........................................97 timing diagrams for x288-configured using up to eight m7040n devices . . ................98 latencyofsearchfromcyclescanddtosramaccesscycle,288-bit(table45.)........101 shiftofssfandssvfromsadr(table46.)........................................101 288-bitsearchontablesconfiguredasx288usingupto31m7040ndevices..........101 hit/missassumption(table47.)..................................................103 hardwarediagramforatablewith31devices(figure74.) ............................103 hardwarediagramforablockofuptoeightdevices(figure75.) .......................104 x288tablewith31devices(figure76.)............................................105 timing diagrams for x288 using up to 31 m7040n devices ............................106 latencyofsearchfromcyclescanddtosramaccesscycle,288-bit(table48.)........117 shiftofssfandssvfromsadr(table49.)........................................117 mixed searches. . . ............................................................117 tablesconfiguredwithdifferentwidthsusinganm7040nwithcfg_llow ..............117 tablesconfiguredtodifferentwidthsusinganm7040nwithcfg_lhigh................117 timingdiagramformixedsearch(onedevice)(figure88.)..........................118 multi-widthconfigurationsexample(figure89.).....................................119 searcheswithcfg_lsethigh(table50.).........................................119 lramandldevdescription...................................................119 learncommand ..............................................................120 timingdiagramoflearn:tlsz=00(figure90.)...................................121 timingdiagramoflearn:tlsz=01(exceptonthelastdevice)(figure91.).............122 timingdiagramoflearnondevice7:tlsz=01(figure92.).........................123 latencyofsramwritecyclefromsecondcycleoflearninstruction(table51.)........123
m7040n 6/159 depth-cascading . ............................................................124 depth-cascadinguptoeightdevices(oneblock) ...................................124 depth-cascading up to 31 devices (4 blocks) .......................................124 depth-cascadingtogenerateafullsignal.......................................124 depth-cascadingtoformasingleblock(figure93.) .................................125 depth-cascadingfourblocks(figure94.)..........................................126 full generation in a cascaded table (figure 95.) ..................................127 sram addressing . ............................................................128 generating an sram bus address (table 52.) .......................................128 srampioaccess ............................................................128 sramreadwithatableofonedevice .........................................128 sramreadaccessforonedevice(figure96.) ....................................129 sramreadwithatableofuptoeightdevices ..................................130 tablewitheightdevices(figure97.)..............................................131 sramreadthroughdevice0inablockofeightdevices(figure98.)...................132 sramreadtimingfordevice7inablockofeightdevices(figure99.) .................133 sramreadwithatableofupto31devices.....................................134 table of 31 devices made of four blocks (figure 100.) ................................135 sram read through device 0 in a bank of 31 devices (device 0 timing) (figure 101.) . . ...136 sram read through device 0 in a bank of 31 devices (device 30 timing) (figure 102.) . ...137 sramwritewithatableofonedevice.........................................138 sramwriteaccessforonedevice(figure103.) ..................................139 sramwritewithatableofuptoeightdevices..................................140 tablewitheightdevices(figure104.).............................................141 sram write through device 0 in a block of eight devices (figure 105.) . . ...............142 sramwritetimingfordevice7inablockofeightdevices(figure106.)................143 sramwritewithtable(s)ofupto31devices ...................................144 table of 31 devices (four blocks) (figure 107.). . . ...................................145 sram write through device 0 in a bank of 31 devices (device 0 timing) (figure 108.). . ...146 sram write through device 0 in a bank of 31 devices (device 30 timing) (figure 109.). ...147 jtag(1149.1)testing ..........................................................148 supportedoperations(table53.).................................................148 tapdeviceidregister(table54.) ...............................................148 partnumbering ..............................................................149 package mechanical information . . . .........................................150 appendix......................................................................152 revisionhistory..............................................................158
7/159 m7040n description overview st microelectronics, inc.s m7040n search en- gine incorporates patent-pending associative pro- cessing technology? (apt) and is designed to be a high-performance, pipelined, synchronous, 64k-entry network database search engine. the m7040n database entry size can be 72 bits, 144 bits, or 288 bits. in the 72-bit entry mode, the size of the database is 64k entries. in the 144-bit mode, the size of the database is 32k entries, and in the 288-bit mode, the size of the database is 16k entries. the m7040n is configurable to sup- port multiple databases with different entry sizes. the 36-bit entry table can be implemented using the global mask registers (gmrs) building-data- base size of 128k entries with a single device. performance the search engine can sustain 100 million trans- actions per second when the database is pro- grammed or configured as 72 or 144 bits. when the database is programmed to have an entry size of 36 or 288 bits, the search engine will perform at 50 million transactions per second. stms m7040n can be used to accelerate network proto- cols such as longest-prefix match (cidr), arp, mpls, and other layer 2, 3, and 4 protocols. applications this high-speed, high-capacity search engine can be deployed in a variety of networking and com- munications applications. the performance and features of the m7040n make it attractive in appli- cations such as enterprise lan switches and rout- ers and broadband switching and/or routing equipment supporting multiple data rates at ocC 48 and beyond. the search engine is designed to be scalable in order to support network database sizes to 3968k entries specifically for environ- ments that require large network policy databases. figure 4, page 10 shows the block diagram for the m7040n device. table 1. product range figure 2. switch/router implementation using the m7040n part number operating supply voltage operating i/o voltage speed temperature range m7040n-100za1 1.65v 2.5 or 3.3v 100mhz commercial m7040n-083za1 1.5v 2.5 or 3.3v 83mhz commercial m7040n-066za1 1.5v 2.5 or 3.3v 66mhz commercial program memory switch fabric switch processor network line interfaces system bus host asic sram bank search engine ai04272
m7040n 8/159 table 2. signal names note: 1. signal types are: i = input only; i/o = input or output; o = output; and t = tristate see descriptions for connection diagram (figure 3, page 9), page 152 for individual connection details. 2. in the previous versions of this specification, this signal was called, clk_out. 3. in previous versions of this specification, this signal was called, pll_bypass. 4. ack and eot signals require a weak, external pull-down resistor of 47 k or 100 k . symbol type (1) description clocks and reset clk_mode i clock mode clk2x_clk1x i master clock phs_l i phase test_co (2) i test output (st use only) test i test input (st use only) test_fm i test input (st use only) rst_l i reset test_pb (3) i test input (st use only) cfg_l i configuration command and dq bus cmd[10:0] i command bus cmdv i command valid dq[71:0] i/o address/data bus ack (4) t read acknowledge eot (4) t end of transfer ssf t search successful flag ssv t search successful flag valid multi_hit o multiple hit flag high_speed i 100mhz indicator clktune[3:0] i pll tuner sram interface sadr[23:0] t sram address ce_l t sram chip enable we_l t sram write enable oe_l t sram output enable ale_l t address latch enable cascade interface lhi[6:0] i local hit in lho[1:0] o local hit out bhi[2:0] i block hit in bho[2:0] o block hit out fuli[6:0] i full in fulo[1:0] o full out full o full flag device identification id[4:0] i device identification supplies v dd n/a chip core supply (1.5v for 66 and 83msps; 1.65 for 100msps) v ddq n/a chip i/o supply (2.5 or 3.3v) test access port tdi i test access port s test data in tck i test access port s test clock tdo t test access port s test data out tms i test access port s test mode select trst_l i test access port s reset
9/159 m7040n figure 3. connections sadr 8 sadr 13 sadr 11 sadr 14 sadr 17 sadr 20 sadr 10 sadr 19 sadr 18 sadr 21 sadr 22 clk_ mode clk1x/ clk2x sadr 23 sadr 15 sadr 5 sadr 6 sadr 7 sadr 9 sadr 12 sadr 16 sadr 2 sadr 1 sadr 3 sadr 0 sadr 4 nc1 nc2 full eot ack nc3 nc5 nc6 nc4 lhi6 lhi5 lhi4 lhi1 lhi0 lho0 lho1 bhi0 bho0 bho1 bho2 fuli0 fulo0 fulo1 fuli2 fuli1 fuli4 fuli3 fuli5 fuli6 bhi2 bhi1 lhi2 lhi3 nc7 nc8 v ddq v ss v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ss v ss v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v dd v dd v dd v dd v ddq v ddq v ddq v ddq v ddq v ddq v ddq v dd v dd v dd v dd v dd v dd v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v dd v ddq v ddq v ddq v ddq v dd v dd v dd v dd v ddq v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v dd v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd cmd8 cmd7 cmd5 cmd2 cmd3 cmd1 cmd10 cmd6 cmd9 cmd4 cmd0 cmdv dq17 dq15 dq13 dq11 dq9 dq1 dq5 dq7 dq21 dq27 dq31 dq33 dq29 dq25 dq23 dq19 dq35 dq37 dq43 dq53 dq57 dq61 dq63 dq67 dq59 dq55 dq49 dq45 dq64 dq62 dq70 dq60 dq66 dq58 dq56 dq52 dq50 dq48 dq46 dq44 dq42 dq38 dq30 dq36 dq32 dq34 dq28 dq20 dq24 dq22 dq16 dq18 dq8 dq0 dq2 dq4 dq12 dq10 dq14 dq6 dq26 dq40 dq68 dq54 dq51 dq41 dq39 dq47 dq65 dq71 dq69 dq3 tdo tms tck tdi id0 id2 id3 id1 id4 test_ fm test_ pb high_ speed test multi_ hit clk tune2 clk tune3 clk tune0 clk tune1 test_ co we_l oe_l ale_l ce_l phs_l cfg_l ssf ssv rst_l trst_ l ai04646 af ad ae ac ab aa y w v u t r p n l m k j h g f e d c b a af ad ae ac ab aa y w v u t r p n l m k j h g f e d c b a 1234 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1234567 89 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
m7040n 10/159 figure 4. m7040n block diagram ai04645 comparand registers[15:0] global mask registers [15:0] information and command register burst read register burst write register next free address register search successful index registers [7:0] (all registers are 72-bit-wide) ta p controller pipeline and sram control arbitration logic command decode and pio access compare/pio data phs_l clk1x_clk2x rst_l dq [71:0] cmd [10:0] cmdv ack eot cmd compare/pio data address decode priority encode match logic configurable as 128k x 36 64k x 72 32k x 144 16k x 288 data array configurable as 128k x 36 64k x 72 32k x 144 16k x 288 mask array full logic full [6:0] full fulo [1:0] id [4:0] lhi [6:0] bhi [2:0] ssf ssv lho [1:0] bho [2:0] ta p sadr [23:0] oe_l we_l ce_l ale_l clk_mode
11/159 m7040n maximum rating stressingthedeviceabovetheratinglistedinthe absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 3. absolute maximum ratings note: 1. soldering temperature not to exceed 260 c for 10 seconds (total thermal budget not to exceed 150 c for longer than 30 seconds). symbol parameter value unit t stg storage temperature (v dd off) C 0to70 c t sld (1) lead solder temperature for 10 seconds 235 c v dd v dd operating supply voltage clk1x = 83mhz 1.575 v clk1x = 100mhz 1.733 v v ddq v ddq voltage for i/o (3.3v) 3.5 v v ddq v ddq voltage for i/o (2.5v) 2.625 v v ddq v ddq voltage for i/o (1.8v) 1.9 v i o output current 100 ma
m7040n 12/159 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 4. dc and ac measurement conditions note: 1. maximum allowable applies to overshoot only (v ddq is 3.3v supply). 2. minimum allowable applies to undershoot only. sym parameter min max units v dd v dd operating supply voltage clk1x = 83mhz 1.425 1.575 v clk1x = 100mhz 1.568 1.733 v v ddq v ddq voltage for i/o (3.3v) 3.1 3.5 v v ddq v ddq voltage for i/o (2.5v) 2.375 2.625 v v ddq v ddq voltage for i/o (1.8v) 1.7 1.9 v t a ambient operating temperature 0 70 c supply voltage tolerance C 5+5% input pulse levels (v ddq = 3.3v) gnd to 3.0 v input pulse levels (v ddq = 2.5v) gnd to 2.5 v input pulse levels (v ddq = 1.8v) gnd to 1.8 v input rise and fall times at 0.3v and 2.7v (v ddq = 3.3v) 2ns (see figure 6, page 13) ns input rise and fall times at 0.25v and 2.25v (v ddq = 2.5v) 2ns (see figure 6, page 13) ns input timing reference levels (v ddq = 3.3v) 1.5 v input timing reference levels (v ddq = 2.5v) 1.25 v input timing reference levels (v ddq = 1.8v) 0.9 v output timing reference levels (v ddq = 3.3v) 1.5 v output timing reference levels (v ddq = 2.5v) 1.25 v output timing reference levels (v ddq = 1.8v) 0.9 v output load (see figure 5 and figure 7, page 13) v
13/159 m7040n figure 5. m7040n 1.8, 2.5, or 3.3v ac testing load figure 6. m7040n 1.8, 2.5, or 3.3v input waveform figure 7. m7040n 1.8, 2.5, or 3.3v i/o output load equivalent note: 1. output loading is specified with cl = 5pf as in figure 7. transition is measured at 200 mv from steady-state voltage. 2. theloadusedforv oh ,v ol testing is shown in figure 7. c l v l = 1.25v for v ddq = 2.5v v l = 1.50v for v ddq = 3.3v 50 z 0 = 50 d out ai04751 +2.5v v ddq = 2.5v / +3.0v v ddq = 3.3v 90% 10% 90% 10% gnd ai04752 208 for v ddq = 2.5v 158 for v ddq = 3.3v 192 for v ddq = 2.5v 175 for v ddq = 3.3v ai04753 5pf q v ddq for hi-z and v ol /v oh (1, 2)
m7040n 14/159 table 5. capacitance note: 1. effective capacitance measured with power supply. sampled only, not 100% tested. 2. at 25 c, f = 1mhz. 3. outputs deselected. table 6. dc characteristics note: 1. valid for ambient operating temperature: t a =0to70 c; v dd =1.5v. symbol parameter test condition (1,2) min max unit c in input capacitance v in =0v 6pf c io (3) output capacitance v out =0v 6pf sym parameter test condition (1) min max unit i li input leakage current v ddq =v ddq (max), v in = 0 to v ddq (max) C 10 +10 a i lo output leakage current v ddq =v ddq (max), v in = 0 to v ddq (max) C 10 +10 a v il input low voltage (v ddq = 3.3v) C 0.3 0.8 v v ih input high voltage (v ddq = 3.3v) 2.0 v ddq +0.3 v v il input low voltage (v ddq = 2.5v) C 0.3 0.7 v v ih input high voltage (v ddq = 2.5v) 1.7 v ddq +0.3 v v il input low voltage (v ddq = 1.8v) C 0.3 0.35 * v ddq v v ih input high voltage (v ddq = 1.8v) 0.7 * v ddq v ddq +0.3 v v ol output low voltage (v ddq = 3.3v) v ddq =v ddq (min), i ol = 16ma 0.4 v v oh output high voltage (v ddq = 3.3v) v ddq =v ddq (min), i oh = 8ma 2.4 v v ol output low voltage (v ddq = 2.5v) v ddq =v ddq (min), i ol =8ma 0.4 v v oh output high voltage (v ddq = 2.5v) v ddq =v ddq (min), i oh = 8ma 2.0 v v ol output low voltage (v ddq = 1.8v) v ddq =v ddq (min), i ol =8ma 0.45 v v oh output high voltage (v ddq = 1.8v) v ddq =v ddq (min), i oh = 8ma v dd C 0.45 v i dd1 1.65v supply current at v dd (max) 100mhz search rate 6.0 a 1.5v supply current at v dd (max) 83mhz search rate 5.0 a 1.5v supply current at v dd (max) 66mhz search rate 4.0 a i dd2 3.3v supply current at v dd (max) 100mhz search rate, i out =0ma 350 ma 83mhz search rate, i out =0ma 300 ma 66mhz search rate, i out =0ma 240 ma i dd2 2.5v supply current at v dd (max) 100mhz search rate, i out =0ma 350 ma 83mhz search rate, i out =0ma 300 ma 66mhz search rate, i out =0ma 240 ma
15/159 m7040n figure 8. ac timing waveforms with clk2x cycle 1 cycle 0 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 12 cycle 9 cycle 11 clk2x signal group 0 signal group 2 signal group 3 signal group 4 signal group 5 clk ai04748 signal group 0: phs_l, rst_l signal group 1: dq, cmd, cmdv signal group 2: lhi, bhi, fuli signal group 3: lho, bho, fulo, full signal group 4: sadr, ce_l, oe_l, we_l, ale_l, ssf, ssv signal group 5: dq, ack, eot ticsch tckhov tckhsv tckhshz tckhslz tckhov tihch tisch tckhdz tckhdv signal group 1 tichch tihch tisch tisch tihch tihch
m7040n 16/159 figure 9. ac timing waveforms with clk1x cycle 1 cycle 0 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 12 cycle 9 cycle 11 clk1x signal group 0 signal group 2 signal group 3 signal group 4 signal group 5 clk ai04749 signal group 0: phs_l, rst_l signal group 1: dq, cmd, cmdv signal group 2: lhi, bhi, fuli signal group 3: lho, bho, fulo, full signal group 4: sadr, ce_l, oe_l, we_l, ale_l, ssf, ssv signal group 5: dq, ack, eot ticsch tckhov tckhsv tckhshz tckhslz tckhov tihch tisch tckhdz tckhdv signal group 1 tichch tisch tisch tihch tihch
17/159 m7040n table 7. ac timing parameters with clk2x note: 1. valid for ambient operating temperature: t a =0to70 c; v dd =1.5v. 2. values are based on 50% signal levels. 3. based on an ac load of cl = 30pf (see figure 5, figure 6, and figure 7, page 13). 4. these parameters are sampled and not 100% tested, and are based on an ac load of 5pf. row sym m7040n- 066 m7040n- 083 m7040n- 100 unit description (1) (v ddq = 3.3v, 2.5v) (v ddq = 3.3v, 2.5v, 1.8v) (v ddq = 3.3v, 2.5v) min max min max min max 1 f clock 40 133 40 166 40 200 mhz clk2x frequency 2 t clok 0.5 0.5 0.5 ms pll lock time 3 t ckhi 3.0 2.4 2.0 ns clk2x high pulse (2) 4 t cklo 3.0 2.4 2.0 ns clk2x low pulse (2) 5 t isch 2.5 1.8 1.5 ns input setup time to clk2x rising edge (2) 6 t ihch 0.6 0.6 0.5 ns input hold time to clk2x rising edge (2) 7 t icsch 4.2 3.5 3.0 ns cascaded input setup time to clk2x rising edge (2) 8 t ichch 0.6 0.6 0.5 ns cascaded input hold time to clk2x rising edge (2) 9 t ckhov 8.5 7.0 6.5 ns rising edge of clk2x to lho, fulo, bho, full valid (3) 10 t ckhdv 9.0 7.5 7.0 ns rising edge of clk2x to dq valid (3) 11 t ckhdz 8.5 7.0 6.5 ns rising edge of clk2x to dq high-z (4) 12 t ckhsv 9.0 7.5 7.0 ns rising edge of clk2x to sram bus valid (3) 13 t ckhshz 6.5 6.0 5.5 ns rising edge of clk2x to sram bus high-z (4) 14 t ckhslz 7.0 6.5 6.0 ns rising edge of clk2x to sram bus low-z (4)
m7040n 18/159 table 8. ac timing parameters with clk1x note: 1. valid for ambient operating temperature: t a =0to70 c; v dd =1.5v. 2. values are based on 50% signal levels and a 50/50% duty cycle of clk1x. 3. based on an ac load of cl = 30pf (see figure 5, figure 6, and figure 7, page 13). 4. these parameters are sampled and not 100% tested, and are based on an ac load of 5pf. row sym m7040n- 066 m7040n- 083 m7040n- 100 unit description (1) (v ddq = 3.3v, 2.5v, 1.8v) (v ddq = 3.3v, 2.5v, 1.8v) (v ddq = 3.3v, 2.5v) min max min max min max 1 f clock 20 66 20 83 20 100 mhz clk1x frequency 2 t clok 0.5 0.5 0.5 ms pll lock time 3 t ckhi 6.75 5.4 4.5 ns clk1x high pulse (2) 4 t cklo 6.75 5.4 4.5 ns clk1x low pulse (2) 5 t isch 2.5 1.8 1.5 ns input setup time to clk1x edge (2) 6 t ihch 0.6 0.6 0.5 ns input hold time to clk1x edge (2) 7 t icsch 4.2 3.5 3.0 ns cascaded input setup time to clk1x rising edge (2) 8 t ichch 0.6 0.5 0.5 ns cascaded input hold time to clk1x rising edge (2) 9 t ckhov 8.5 7.0 6.5 ns rising edge of clk1x to lho, fulo, bho, full valid (3) 10 t ckhdv 9.0 7.5 7.0 ns rising edge of clk1x to dq valid (3) 11 t ckhdz 8.5 7.0 6.5 ns rising edge of clk1x to dq high-z (4) 12 t ckhsv 9.0 7.5 7.0 ns rising edge of clk1x to sram bus valid (3) 13 t ckhshz 6.5 6.0 5.5 ns rising edge of clk1x to sram bus high-z (4) 14 t ckhslz 7.0 6.5 6.0 ns rising edge of clk1x to sram bus low-z (4)
19/159 m7040n operation command bus and dq bus cmd[10:0] carries the command and its associat- ed parameter. dq[71:0] is used for data transfer to and from the database entries. these entries com- prise a data and a mask field that are organized as data and mask arrays. the dq bus carries the search data (of the data and mask arrays and in- ternal registers) during the search command as well as the address and data during read and/or write operations. the dq bus can also carry the address information for the flow-through accesses to the external srams and/or ssrams. database entry (data array and mask array) each database entry comprises a data and a mask field. the resultant value of the entry is 1, 0, or x (don t care), depending on the value in the data and mask bits. the on-chip priority encoder se- lects the first matching entry in the database that is nearest to location 0. arbitration logic when multiple search engines are cascaded to create large databases, the data being searched is presented to all search engines simultaneously in the cascaded system. if multiple matches occur within the cascaded devices, arbitration logic on the search engines will enable the winning device (with a matching entry that is closest to address 0 of the cascaded database) to drive the sram bus. pipeline and sram control pipeline latency is added to give enough time to a cascaded system s arbitration logic to determine the device that will drive the index of the matching entry on the sram bus. pipeline logic adds laten- cy to both the sram access cycles and the ssf and ssv signals to align them to the host asic re- ceiving the associated data. full logic bit[0] in each of the 72-bit entries has a special purpose for the learn command (0 = empty, 1 = full). when all the data entries have bit[0] = 1, the database asserts the full flag, indicating all the search engines in the depth-cascaded array are full. connection descriptions clock mode (clk_mode). this signal allows the selection of clock input to the clk1x/clk2x pin. if the clk_mode pin is low, clk2x must be supplied on that pin. phs_l must also be sup- plied. if the clk_mode pin is high, clk1x must be supplied on the clk2x/clk1x pin, and the phs_l signal is not required. when the clk_mode is high, phs_l is unused and should be externally grounded. master clock (clk2x/clk1x). depending on the clk_mode pin, either the clk2x or the clk1x must be supplied. m7040n samples con- trol and data signals on both the edges of clk1x if clk1x is supplied. m7040n samples all the data and control pins on the positive edge of clk2x if the clk2x and phs_l signals are supplied. all signals are driven out of the device on the rising edge of clk1x if clk1x is supplied, and are driv- en on the rising edge of clk2x (when phs_l is low) if clk2x is supplied. phase (phs_l). this signal runs at half the fre- quency of clk2x and generates an internal clock from clk2x (see figure 10, page 21). test output (test_co). this is test output and will stay unconnected in the application of the de- vice. test input (test). this signal should be con- nected to ground. test input (test_fm). this signal should be connected to ground. reset (rst_l). driving rst_l low initializes the device to a known state. test input (test_pb). this signal should be connected to ground. configuration. when cfg_l is low, m7040n will operate in backward compatibility mode with m7010 and m7020. when cfg_l is low, the cmd[10:9] should be externally grounded. with cfg_l low, the device will behave identically with m7010 and m7020, and the new feature added to m7040n will be disabled. when cfg_l is high, the additional command cmd[10:9] can be used and the following addition- al features will be supported: 1. 16 pairs of global masks are supported instead of eight; 2. parallel write to the data and mask arrays is supported (see parallel write, page 38); and 3. configuring tables of up to three different widths does not require table identification bits in the data array, thus saving two bits from each 72-bit
m7040n 20/159 command bus (cmd[10:0]. [1:0] specifies the command; [10:2] contains the command parame- ters. the descriptions of individual commands ex- plains the details of the parameters. the encoding of commands based on the [1:0] field are: C 00: pio read C 01: pio write C 10: search C 11: learn command valid ( cmdv) . qualifies the cmd bus as follows: C 0: no command C 1: command address/data bus ( dq[71:0]) . carries the read and write address as well as the data during register, data, and mask array operations. it car- ries the compare data during search operations. it also carries the sram address during sram pio accesses. read acknowledge (ack). indicates that valid data is available on the dq bus during register, data, and mask array read operations, or the data is available on the sram data bus during sram read operations. note: ack signals require a weak external pull- down resistor such as 47 or 100 k . end of transfer (eot). indicates the end of burst transfer during read or write burst oper- ations. note: eot signals require a weak external pull- down resistor such as 47 k or 100 k . search successful flag (ssf). when assert- ed, this signal indicates that the device is the glo- bal winner in a search operation. search successful flag valid (ssv). when asserted, this signal qualifies the ssf signal. multiple hit flag (multi_hit). when asserted, this signal indicates that there is more than one lo- cation having a match on this device. high speed (high_speed). when this signal is high, the device will run up to 100mhz and perform 100 million searches per second. however, in this mode, a tlsz value of '00' is not supported in a system of a single device. furthermore, the device will only support a tlsz of '00' and '01' if more than one device is cascaded to form database ta- bles. clock tune [3:0] (clk_tune[3:0]). these test pins should be set to logic level 1001. sram address (sadr[23:0]). this bus con- tains address lines to access off-chip srams that contain associative data. see table 52, page 128 for the details of the generated sram address. in a database of multiple m7040ns, each corre- sponding bit of sadr from all cascaded devices must be connected. sram chip enable (ce_l). this is chip enable control for external srams. in a database of mul- tiple m7040ns, ce_l of all cascaded devices must be connected. this signal is then driven by only one of the devices. sramwriteenable(we_l). this is write en- able control for external srams. in a database of multiple m7040ns, we_l of all cascaded devices must be connected together. this signal is then driven by only one of the devices. sram output enable (oe_l). this is output enable control for external srams. only the last device drives this signal (with the lram bit set). address latch enable (ale_l). when this sig- nal is low, the addresses are valid on the sram address bus. in a database of multiple m7040ns, the ale_l of all cascaded devices must be con- nected. this signal is then driven by only one of the devices. local hit in (lhi[6:0]). these pins depth-cas- cade the device to form a larger table size. one signal of this bus is connected to the lho[1] or lho[0] of each of the upstream devices in a block. connect all unused lhi pins to a logic '0.' (for more information, see depth-cascading, page 124.) local hit out (lho[1:0]). lho[1] and lho[0] are the same logical signal. lho[1] or lho[0] is connected to one input of the lhi bus of up to four downstream devices (in a block that contains up to eight devices). (for more information, see depth-cascading, page 124.) block hit in (bhi[2:0]). inputs from the previous bho[2:0] are tied to the bhi[2:0] of the current de- vice (see depth-cascading, page 124). in a four-block system, the last block can contain only seven devices because the id code 11111 is used for broadcast access. block hit out (bho[2:0]). these outputs from the last device in a block are connected to the bhi[2:0] inputs of the devices in the downstream blocks (see depth-cascading, page 124).
21/159 m7040n full in (fuli[6:0]). each signal in this bus is con- nected to fulo[0] or fulo[1] of an upstream de- vice to generate the full signal for the depth- cascaded block. for more information, see depth-cascading, page 124 to generate full for a block section. full out (fulo[1:0]). fulo[1] and fulo[0] are the same logical signal. one of these two signals must be connected to the fuli of up to four down- stream devices in a depth-cascaded table. bit [0] in the data array indicates if the entry is full (1) or empty (0).this signal is asserted if all of the bits in the data array are '1s.' refer to depth-cascading to generate a full signal, page 124. full flag (full). when asserted, this signal in- dicates that the table consisting of many depth- cascaded devices is full. device identification (id[4:0]). the binary-en- coded device id for a depth-cascaded system starts at 00000 and goes up to 11110. 11111 is re- served for a special broadcast address that se- lects all cascaded search engines in the system. on a broadcast read-only, the device with the ldev bit set to '1' responds. chip core supply (v dd ). this is equal to 1.5v. chip i/o supply (v ddq ). this is equal to either 2.5 or 3.3v. test data in (tdi). this is the test access port s test data in. test clock (tck). this is the test access port s test clock. test data out (tdo). this is the test access port s test data out. test mode select (tms). this is the test ac- cess port s test mode select. test reset (trst_l). this is the test access port s test reset. clocks if the clk_mode pin is low, m7040n receives the clk2x and phs_l signals. it uses the phs_l sig- nal to divide clk2x and generate an internal clock (clk), as shown in figure 10. the m7040n uses clk2x and clk for internal operations. if the clk_mode pin is high, the m7040n receives the clk1x only. the m7040n uses an internal pll to double the frequency of clk1x and then divides that clock by two to generate a clk for internal op- erations, as shown in figure 11. note: for the purpose of showing timing dia- grams, all such diagrams in this document will be shown in clk2x mode. for a timing diagram in clk1x mode, the following substitution can be made (see figure 12). figure 10. clocks (clk2x and phs_l) note: any reference to clk cycles means 1 cycle of the signal, clk. 1. clk is an internal signal. figure 11. clocks (clk1x) 1. clk is an internal signal. clk2x phs_l cl k (1) ai04750 clk1x cl k (1) ai04665
m7040n 22/159 figure 12. clocks for all timing diagrams pll usage when the device first powers up, it takes 0.5 ms to lock the internal phase-lock loop (pll). during this locking of the pll, in addition to 32 extra clk1x cycles in clk1x mode and 64 extra cycles in clk2x mode, the rst_l must be held low for proper initialization of the device. setup and hold requirements will change in clk1x mode if the duty cycle of the clk1x is varied. all signals into the device in clk1x mode are sampled by a clock that is generated by multiplying clk1x by two. since pll has a locking range, the device will only work between the range of frequencies specified in the timing specification section. registers all registers in the m7040n are 72 bits wide. the m7040n contains 16 pairs of comparand storage registers, 16 pairs of global mask registers (gmrs), eight search successful index registers and one each of command, information, burst read, burst write, and next-free address regis- ters. table 9 provides an overview of all the m7040n registers. the registers are ordered in as- cending address order. each register group is then described in the following subsections. table 9. register overview clk2x phs_l clk1x ai04666 (use for clk1x mode) (use for clk1x mode) address abbreviation type name 0 C 31 comp0 C 31 r 32 comparand registers. stores comparands from the dq bus for learning later. 32 C 47, 96 C 111 masks rw 16 global mask registers pairs. 48 C 55 ssr0 C 7 r 8 search successful index registers. 56 command rw command register. 57 info r information register. 58 rburreg rw burst read register. 59 wburreg rw burst write register. 60 nfa r next free address register. 61 C 63 CC reserved
23/159 m7040n comparand registers the device contains 32 72-bit comparand regis- ters (16 pairs) dynamically selected in every search operation to store the comparand pre- sented on the dq bus. the learn command will later use these registers when executed. the m7040n stores the search command scyclea comparand in the even-numbered register and the cycle b comparand in the odd-numbered register, as shown in figure 13. figure 13. comparand register selection during search and learn instructions mask registers the device contains 32 72-bit global mask regis- ters (16 pairs) dynamically selected in every search operation to select the search subfield. the addressing of these registers is explained in figure 14. the four-bit gmr index supplied on the command (cmd) bus can apply 16 pairs of global masks during the search and write opera- tions, as shown below. note: in 72-bit search and write operations, the host asic must program both the even and odd mask registers with the same values. each mask bit in the gmrs is used during search and write operations. in search op- erations, setting the mask bit to '1' enables com- pares; setting the mask bit to '0' disables compares (forced match) at the corresponding bit position. in write operations to the data or mask array, setting the mask bit to '1' enables writes; setting the mask bit to '0' disables writes at the corresponding bit position. figure 14. addressing the global masks register array 143 0 72 72 1 0 3 2 5 4 7 6 30 31 0 15 1 a ddre ss index ai04667 143 0 72 72 1 0 3 2 5 4 7 6 9 8 11 10 13 12 15 14 0 1 6 7 2 5 4 3 a ddre ss index ai04668 search and write command global mask selection 16 18 20 22 24 26 28 17 19 21 23 25 27 29 30 31 8 9 10 11 12 13 14 15
m7040n 24/159 search-successful registers (ssr[0:7]) the device contains eight search successful reg- isters (ssrs) to hold the index of the location where a successful search occurred. the format of each register is described in table 10. the search command specifies which ssr stores the index of a specific search command in cy- cle b of the search instruction. subsequently, the host asic can use this register to access that data array, mask array, or external sram using the index as part of the indirect access address (see table 20, page 34 and table 23, page 37) . the device with a valid bit set performs a read or write operation. all other devices suppress the operation. table 10. search-successful register (ssr) description field range initial value description index [15:0] x index. this is the address of the 72-bit entry where a successful search occurs. the device updates this field only when a search is successful. if a hit occurs in a 144-bit entry-size quadrant, the lsb is '0.' if a hit occurs in a 288-bit entry size quadrant, the two lsbs are '00.' this index updates if the device is either a local or global winner in a search operation. C [30:16] 0 reserved. valid [31] 0 valid. during search operation in a depth-cascaded configuration, the device that is a global winner in a match sets this bit to '1.' this bit updates only when the device is a global winner in a search operation. C [71:32] 0 reserved.
25/159 m7040n the command register table 11. command register field descriptions field range initial value description srst [0] 0 software reset. if '1,' this bit resets the device, with the same effect as the hardware reset. internally, it generates a reset pulse lasting for eight clk cycles. this bit automatically resets to a '0' the reset cycle has completed. deve [1] 0 device enable. if '0,' it keeps the sram bus (sadr, we_l, ce_l, oe_l, and ale_l), ssf, and ssv signals in 3-state condition and forces the cascade interface output signals lho[1:0] and bho[2:0] to '0.' it also keeps the dq bus in input mode. the purpose of this bit is to make sure that there are no bus contentions when the devices power up in the system. tlsz [3:2] 01 table size. the host asic must program this field to configure the chips into a table of a certain size. this field affects the pipeline latency of the search and learn operations as well as the read and write accesses to the sram (sadr[23:0], ce_l, oe_l, we_l, ale_l, ssv, ssf, and ack). once programmed, the search latency stays constant. latency # clk cycles with high_speed low 00: 1 device 4 01: 2-8 devices 5 10: 9-31 devices 6 11: reserved latency # clk cycles with high_speed high 00: not supported 01: 1 devices 5 10: 2-31 devices 6 11: reserved hlat [6:4] 000 latency of hit signals. this field adds latency to the ssf and ssv signals during search, and ack signal during sram read access by the following number of clk cycles. 000: 0 100: 4 001: 1 101: 5 010: 2 110: 6 011: 3 111: 7 ldev [7] 0 last device in the cascade. when set, this is the last device in the depth-cascaded table and is the default driver for the ssf and ssv signals. in the event of a search failure, the device with this bit set drives the hit signals as follows: ssf = 0, ssv = 1 during non-search cycles, the device with this bit set drives the signals as follows: ssf = 0, ssv = 0
m7040n 26/159 the information register table 12. information register field descriptions lram [8] 0 last device on this sram bus. when set, this device is the last device on this sram bus in the depth-cascaded table and is the default driver for the sadr, ce_l, we_l, and ale_l signals. in cycles where no m7040n device in a depth-cascaded table drives these signals, this device drives the signals as follows: sadr = ffffff, ce_l = 1 we_l = 1 ale_l = 1 oe_l is always driven by the device for which this bit is set. cfg [24:9] 0000 0000 0000 0000 database configuration. the device is internally divided into eight quadrants of 8k x 72, each of which can be configured as 8k x 72, 4k x 144, or 2k x 288 as follows: 00: 8k x 72 01: 4k x 144 10: 2k x 288 11: low power, partition not used for search bits [10:9] apply to configuring the 1st quadrant in the address space. bits [12:11] apply to configuring the 2nd quadrant in the address space. bits [14:13] apply to configuring the 3rd quadrant in the address space. bits [16:15] apply to configuring the 4th quadrant in the address space. bits [18:17] apply to configuring the 5th quadrant in the address space. bits [20:19] apply to configuring the 6th quadrant in the address space. bits [22:21] apply to configuring the 7th quadrant in the address space. bits [24:23] apply to configuring the 8th quadrant in the address space. [71:25] 0 reserved. field range initial value description field range initial value description revision [3:0] 0001 revision number. this is the current device revision number. numbers start from one and increment by one for each revision of the device. implementation [6:4] 001 this is the m7040n implementation number. reserved [7] 0 reserved. device id [15:8] 00000100 this is the device identification number. mfid [31:16] 0000_0010_0000_1111 manufacturer id. this field is the same as the manufacturer id and continuation bits in the tap controller. [71:32] reserved.
27/159 m7040n the read burst address register (rburreg) these read burst address register fields must be programmed before burst read. table 13. read burst register description the write burst address register (wburreg) these write burst address register fields must be programmed before burst write. table 14. write burst register description the nfa register bit [0] of each 72-bit data entry is a special bit des- ignated for use in the operation of the learn command. in 72-bit quadrants, the bit[0] indicates whether a location is full (bit set to '1') or empty (bit set to '0'). every write/learn command loads the address of first 72-bit location that contains a '0' in the entry s bit[0]. this is stored in the nfa register (see table 15). if all the bits in a device are set to '1,' the m7040n asserts fulo[1:0] to '1.' in 144-bit-configured quadrants, the lsb of this register is always set to '0.' the host asic must set bit '0' and bit 72 in a 144-bit word to either '0' or '1' to indicate full/empty status. note: both bits (0 and 72) must be set to '0' or '1' (e.g., '10' or '01' settings are invalid). table 15. nfa register field range initial value description adr [15:0] 0 address. this is the starting address of the data array or mask array during a burst read operation. it automatically increments by 1 for each successive read of the data array or mask array. once the operation is complete, the contents of this field must be reinitialized for the next operation. [18:16] reserved. blen [27:19] 0 length of burst access. the device is capable of writing from 4 up to 511 locations in a single burst. the blen decrements automatically. once the operation is complete, the contents of this field must be reinitialized for the next operation. [71:28] reserved. field range initial value description adr [15:0] 0 address. this is the starting address of the data array or mask array during a burst write operation. it automatically increments by 1 for each successive write of the data array or mask array. once the operation is complete, the contents of this field must be reinitialized for the next operation. [18:16] reserved. blen [27:19] 0 length of burst access. the device is capable of writing from 4 up to 511 locations in a single burst. the blen decrements automatically. once the operation is complete, the contents of this field must be reinitialized for the next operation. [71:28] reserved. address 71 - 16 15 - 0 60 reserved index
m7040n 28/159 search engine architecture the m7040n consists of 64k x 72-bit storage cells referred to as data bits. there is a mask cell corre- sponding to each data cell. figure 15 shows the three organizations of the device based on the val- ue of the cfg bits in the command register. during a search operation, the search data bit (s), data array bit (d), mask array bit (m) and the global mask bit (g) are used in the following man- ner to generate a match at that bit position (see table 16, page 29). the entry with all matched bit positions results in a successful search during a search operation. in order for a successful search within a device to make the device the local winner in the search operation, all 72-bit positions must generate a match for a 72-bit entry in 72-bit-configured quad- rants, or all 144-bit positions must generate a match for two consecutive even and odd 72-bit en- tries in quadrants configured as 144 bits, or all 288-bit positions must generate a match for 4 con- secutive entries aligned to 4 entry-page bound- aries of 72-bit entries in quadrants configured as 288 bits. an arbitration mechanism using a cascade bus de- termines the global winning device among the lo- cal winning devices in a search cycle. the global winning device drives the sram bus, ssv, and the ssf signals. in case of a search failure, the devices with the ldev and lram bits set drive(s) the sram bus, ssf, and ssv signals the m7040n device can be configured to contain tables of different widths, even within the same chip. figure 16, page 29 shows a sample configu- ration of different widths. data and mask addressing figure 17, page 29 shows the m7040n data array and mask array addressing procedure. figure 15. m7040n database width configuration data data data masks masks masks 64 k cfg = 0000000000000000 cfg = 0101010101010101 cfg = 1010101010101010 72 144 288 32 k 16 k ai04669
29/159 m7040n table 16. bit position match figure 16. multi-width configuration example figure 17. m7040n data and mask array addressing g m s d match 0xxx1 10xx1 11001 11010 11100 11111 8 k 8 k 4 k 2 k 72 72 144 288 cfg = 10 10 01 01 11 11 00 00 8 k 8 k 72 72 4 k 144 2 k 288 ai04670 inactive (low power) cfg = 0000000000000000 cfg = 1010101010101010 71 0 0 1 2 3 65535 283 0 3 2 1 0 7 6 5 4 65532 65533 65534 65535 72 cfg = 0101010101010101 143 0 1 0 3 2 5 4 7 6 65534 65535 (72-bit configuration) (288-bit configuration) (144-bit configuration) 64 k 16k 32k 72 72 72 72 72 72 ai04671
m7040n 30/159 command codes and parameters a master device, such as an asic controller, is- sues commands to the m7040n using the com- mand valid cmdv signal and the cmd bus. the following subsections describe the functions of the commands. command codes the m7040n implements four basic commands shown in table 17. the command code must be presented to cmd[1:0] while keeping the com- mand valid (cmdv) signal high for two clk2x cy- cles. these two clk2x cycles are designated as cycle a and cycle b when the clk_mode pin is low. in clk2x mode, the controller asic must align the instructions with the phs_l signal. the command code must be presented to cmd[1:0] while keeping the cmdv signal high for one clk1x cycle when the clk_mode pin is high. in clk1x mode the high phase of the clk1x is des- ignated as cycle a and the low phase of the clk1x is designated as cycle b. the cmd[10:2] field passes the parameters of the command in cycles a and b. commands and command parameters table 18, page 31 lists the cmd bus fields that contain the m7040n command parameters as well as their respective cycles. table 17. command codes cmd code command description 00 read reads one of the following: data array, mask array, device registers, or external sram. 01 write writes one of the following: data array, mask array, device registers, or external sram. 10 search searches the data array for a desired pattern using the specified register from the global mask register array and local mask associated with each data cell. 11 learn the device has internal storage for up to 16 comparands that it can learn. the device controller can insert these entries at the next free address (as specified by the nfa register) using the learn instruction.
31/159 m7040n table 18. command parameters note: 1. use only cmd[8:0] and connect the cmd[10:9] to ground with cfg_l low. 2. for a description of cmd[9] and cmd[2] see subsections on search 288-bit configured tables and mixed-size searches with cfg_l high. 3. the 288-bit-configured devices or 288-bit-configured quadrants within devices do not support the learn instruction. cmd (1, 2) cyc 10 9 8 7 6 5 4 3 2 1 0 read ax x sadr [23] sadr [22] sadr [21] 000 0 = single 1 = burst 00 bx x 0 0 0000 0 = single 1 = burst 00 write a global mask register index [3] 0 normal write 1 parallel write sadr [23] sadr [22] sadr [21] global mask register index [2:0] 0 = single 1 = burst 01 b global mask register index [3] 0 normal write 1 parallel write 000 global mask register index [2:0] 0 = single 1 = burst 01 search a global mask register index [3] 72-bit: 0 144-bit: 1 288-bit:x sadr [23] sadr [22] sadr [21] global mask register index [2:0] 72-bit or 144-bit: 0 288-bit: 1 in 1st cycle 0 in 2nd cycle 10 bx successful search register index[2:0] comparand register index 1 0 learn (3) ax x sadr [23] sadr [22] sadr [21] comparand register index 1 1 bx x 0 0 mode 0: 72-bit 1: 144-bit comparand register index 1 1
m7040n 32/159 read command thereadcanbeasinglereadofadataarray,a mask array, an sram, or a register location (cmd[2] = 0). it can be a burst read (cmd[2] = 1) or mask array locations using an internal auto-in- crementing address register (rburadr). table 19, page 34 describes each type of read com- mand. a single-location read operation lasts six cycles, as shown in figure 18, page 33. the burst read adds two cycles for each successive read. the sadr[23:21] bits supplied in the read instruction cycle a drive sadr[23:21] signals during the read of an sram location. the single read operation takes six clk cycles, in the following sequence: C cycle 1: the host asic applies the read in- struction on the cmd[1:0] (cmd[2] = 0), using cmdv = 1, and the dq bus supplies the ad- dress, as shown in table 20, page 34 and table 21, page 35. the host asic selects the m7040n for which id[4:0] matches the dq[25:21] lines. if the dq[25:21] = 11111, the host asic selects the m7040n with the ldev bit set. the host asic also supplies sadr[23:21] on cmd[8:6] in cycle a of the read instruction if the read is directed to the external sram. C cycle 2: the host asic floats dq[71:0] to 3- state condition. C cycle 3: the host asic keeps dq[71:0] in 3- state condition. C cycle 4: the selected device starts to drive the dq[71:0] bus and drives the ack signal from z to low. C cycle 5: the selected device drives the read data from the addressed location on the dq[71:0] bus and drives the ack signal high. C cycle 6: the selected device floats dq[71:0] to 3-state condition and drives the ack signal low. at the termination of cycle 6, the selected device releases the ack line to 3-state condition. the read instruction is complete, and a new opera- tion can begin. note: the latency of the sram read will be dif- ferent than the one described above (see sram pio access, page 128). table 20, page 34 lists and describes the format of the read address for a data array, mask array, or sram. in a burst read operation, the read lasts 4 + 2n clk-cycles (where n stands for the number of accesses in the burst specified by the blen field of the rburreg). table 21, page 35 describes the read address format for the internal registers. figure 19, page 33 illustrates the timing diagram for the burst read of the data or mask array. this operation assumes that the host asic has pro- grammed the rburreg with the starting address (adr) and the length of transfer (blen) before ini- tiating the burst read command. C cycle 1: the host asic applies the read in- struction on the cmd[1:0] (cmd[2] = 1), using cmdv=1 and the address supplied on the dq bus, as shown in table 22, page 35. the host asic selects the m7040n for which id[4:0] matches the dq[25:21] lines. if the dq[25:21] = 11111, the host asic selects the m7040n with the ldev bit set. C cycle 2: the host asic floats dq[71:0] to the 3- state condition. C cycle 3: the host asic keeps dq[71:0] in the 3-state condition. C cycle 4: the selected device starts to drive the dq[71:0] bus and drives ack and eot from z to low. C cycle 5: the selected device drives the read data from the addressed location on the dq[71:0] bus and drives the ack signal high. note: cycles four and five repeat for each addi- tional access until all the accesses specified in the burst length (blen) field of rburreg are complete. on the last transfer, the m7040n drives the eot signal high. C cycle (4 + 2n): the selected device drives the dq[71:0] to 3-state condition and drives the ack and the eot signals low. at the termination of cycle 4 + 2n, the selected de- vice floats the ack line to 3-state condition. the burst read instruction is complete, and a new op- eration can begin (see table 22, page 35 for burst read address formats).
33/159 m7040n figure 18. single location read cycle timing figure 19. burst read of the data and mask arrays (blen = 4) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] ack dq phs_ l ai04672 read cmd[10:2] b a ad dress ff data cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 11 cycle 12 cycle 9 clk2x cmdv cmd[1:0] cmd[10:2] ack eot dq phs_ l ai04673 read b a ad dress ff data0 ff data1 ff data2 ff data3
m7040n 34/159 table 19. read command parameters table 20. data and mask array, sram read address format note: 1. | stands for logical or operation. {} stands for concatenation operator. cmd parameter cmd[2] read command description 0 single read reads a single location of the data array, mask array, external sram, or device registers. all access information is applied on the dq bus. 1 burst read reads a block of locations from the data array or mask array as a burst. the internal register (rburadr) specifies the starting address and the length of the data transfer from the data array or mask array, and it auto-increments the address for each access. all other access information is applied on the dq bus. note: the device registers and external sram can only be read in single-read mode. dq [71:30] dq [29] dq [28:26] dq [25:21] dq [20:19] dq [18:16] dq [15:0] reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 00: data array reserved if dq[29] is '0,' this field carries address of data array location. if dq[29] is '1,' the successful search register id (ssri) specified on dq[28:26] supplies the address of the data array location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1) reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 01: mask array reserved if dq[29] is '0,' this field carries address of mask array location. if dq[29] is '1,' the successful search register id (ssri) specified on dq[28:26] supplies the address of the mask array location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1) reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 10: external sram reserved if dq[29] is '0,' this field carries address of sram location. if dq[29] is '1,' the successful search register id (ssri) specified on dq[28:26] supplies the address of the sram location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1)
35/159 m7040n table 21. read address format for internal registers table 22. read address format for data and mask arrays write command thewritecanbeasinglewriteofadataarray, mask array, register, or external sram location (cmd[2] = 0). it can be a burst write (cmd[2] = 1) using an internal auto-incrementing address register (wburadr) of the data array or mask array locations. a single-location write is a three-cycle operation, shown in figure 20, page 36. the burst write adds one extra cycle for each successive write. the write operation sequence is as follows: C cycle 1a: the host asic applies the write in- struction on the cmd[1:0] (cmd[2] = 0), using cmdv=1 and the address supplied on the dq bus, as shown in table 23, page 37. the host asic also supplies the index to the global mask register to mask the write to the data array or mask array location in {cmd[10], cmd[5:3]}. for sram writes, the host asic must supply the sadr[23:21] on cmd[8:6]. the host asic sets cmd[9] to '0' for the normal write. C cycle 1b: the host asic continues to apply the write instruction to the cmd[1:0] (cmd[2] = 0), using cmdv = 1 and the address supplied on the dq bus. the host asic contin- ues to supply the global mask register index to mask the write to the data or mask array loca- tions in {cmd[10], cmd[5:3]}. the host asic selects the device where id[4:0] matches the dq[25:21] lines, or it selects all the devices when dq[25:21] = 11111. C cycle 2: the host asic drives the dq[71:0] with the data to be written to the data array, mask array, external sram, or register location of the selected device. C cycle 3: idle cycle. at the termination of this cy- cle, another operation can begin. note: the latency of the sram write will be different than the one described above (see sram pio access, page 128). the burst write operation lasts for n + 2 clk cy- cles (where n signifies the number of accesses in the burst as specified in the blen field of the wburreg register, please see figure 21, page 37). this operation assumes that the host asic has programmed the wburreg with the starting ad- dress (adr) and the length of transfer (blen) be- fore initiating the burst write command (see table 25, page 38 for format). the sequence is as fol- lows: C cycle 1a: the host asic applies the write in- struction on the cmd[1:0] (cmd[2] = 1), using cmdv = 1 and the address supplied on the dq bus, as shown in table 25, page 38. the host asic also supplies the index to the global mask register to mask the write to the data or mask ar- ray locations in {cmd[10], cmd[5:3]}. the host asic sets asic sets cmd[9] to '0' for the nor- mal write. C cycle 1b: the host asic continues to apply the write instruction on the cmd[1:0] (cmd[2] = 0), using cmdv = 1 and the address supplied on the dq bus. the host asic contin- ues to supply the global mask register index to mask the write to the data or mask array loca- tions in {cmd[10], cmd[5:3]}. the host asic selects the device where id[4:0] matches the dq[25:21] lines, or it selects all the devices when dq[25:21] = 11111. dq[71:26] dq[25:21] dq[20:19] dq[18:7] dq[6:0] reserved id 11: register reserved register address dq[71:26] dq[25:21] dq[20:19] dq[18:16] dq[15:0] reserved id 00: data array reserved do not care. these 16 bits come from the internal register (rburadr) which increments for each access. reserved id 01: mask array reserved do not care. these 16 bits come from the internal register (rburadr) which increments for each access.
m7040n 36/159 C cycle 2: the host asic drives the dq[71:0] withthedatatobewrittentothedataarrayor mask array location of the selected device. the m7040n writes the data from the dq[71:0] bus only to the subfield that has the corresponding mask bit set to '1' in the global mask register specified by the index {cmd[10], cmd[5:3]} and supplied in cycle 1. C cycles 3 to n + 1: the host asic drives the dq[71:0] with the data to be written to the next data array or mask array location (addressed by the auto-increment adr field of the wburreg register) of the selected device. the m7040n writes the data on the dq[71:0] bus only to the subfield that has the correspond- ing mask bit set to '1' in the global mask register specified by the index {cmd[10], cmd[5:3]} and supplied in cycle 1. the m7040n drives the eot signal low from cycle 3 to cycle n; the m7040n drives the eot signal high in cycle n + 1(nisspecifiedintheblenfieldofthewbur- reg). C cycle n + 2: the m7040n drives the eot signal low. at the termination of the cycle n + 2, the m7040n floats the eot signal to a 3-state, and a new instruction can begin. figure 20. single location write cycle timing cycle 1 cycle 2 cycle 3 cycle 4 cycle 0 clk2x cmdv cmd[1:0] dq phs_ l ai04674 write cmd[10:2] b a ad dress data x
37/159 m7040n figure 21. burst write of the data and mask arrays (blen = 4) table 23. (single) write address format for data and mask arrays or sram note: 1. | stands for logical or operation. {} stands for concatenation operator. dq [71:30] dq [29] dq [28:26] dq [25:21] dq [20:19] dq [18:16] dq [15:0] reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 00: data array reserved if dq[29] is '0,' this field carries the address of the data array location. if dq[29] is '1,' the successful search register specified by dq[28:26] supplies the address of the data array location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1) reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 01: mask array reserved if dq[29] is '0,' this field carries address of the mask array location. if dq[29] is '1,' the successful search register specified by dq[28:26] supplies the address of the mask array location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1) reserved 0: direct 1: indirect successful search register index (applicable if dq[29] is indirect) id 10: external sram reserved if dq[29] is '0,' this field carries address of the data sram location. if dq[29] is '1,' the successful search register specified by dq[28:26] supplies the address of the sram location: {ssr[15:2], ssr[1] | dq[1], ssr[0] | dq[0]} (1) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] eot dq phs_ l ai04675 write cmd[10:2] b a ad dress data0 data1 data2 data3 x
m7040n 38/159 table 24. write address format for internal registers table 25. write address format for data and mask array (burst write) parallel write in order to write the data and mask arrays faster for initialization, testing, or diagnostics, many loca- tions can be written simultaneously in the m7040n device. when cmd[9] is set in cycles a and b of the write command during a write to the data or mask arrays, the address present on dq[10:1] that specifies 64 locations in a device is used and 64 72-bit locations are simultaneously written in ei- ther the data or mask array. search command the m7040n (silicon) search engine can be con- figuredinfourways: 1. 72-bit 2. 144-bit (page ) 3. 288-bit (page ) 4. mixed-sizes on tables configured with differ- ent widths using an m7040n with cfg_l low or cfg_l high (page ) 72-bit configuration with single device the hardware diagram of the search subsystem of a single device is shown in figure 22. figure 23, page 40 shows the timing diagram for a search operation in the 72-bit configuration (cfg = 0000000000000000) for one set of parameters. this illustration assumes that the host asic has programmed tlsz to '00,' hlat to '000,' lram to '1,' and ldev to '1' in the command register. the following is the sequence of operations for a single 72-bit search command. C cycle a: thehostasicdrivescmdvhighand applies the search command code ('10') on cmd[1:0] signals. {cmd[10], cmd[5:3] must be driven with the index to the global mask register pair for use in the search operation. cmd[8:6] signals must be driven with the same bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven with the 72- bit data to be compared. the cmd[2] signal must be driven to logic '0.' C cycle b: the host asic continues to drive cmdv high and applies the search command ('10') on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for stor- ing the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching en- try and the hit flag (see search-successful registers (ssr[0:7]), page 24). the dq[71:0] continues to carry the 72-bit data to be com- pared. note: in the 72-bit configuration, the host asic must supply the same data on dq[71:0] during both cycles a and b. the even and odd pair of gmrs selected for the comparison must be pro- grammed with the same value. dq[71:26] dq[25:21] dq[20:19] dq[18:7] dq[6:0] reserved id 11: register reserved register address dq [71:26] dq [25:21] dq [20:19] dq [18:16] dq [15:0] reserved id 00: data array reserved don t care. these 16 bits come from the internal register (wburadr), which increments with each access. reserved id 01: mask array reserved don t care. these 16 bits come from the internal register (wburadr), which increments with each access.
39/159 m7040n the logical 72-bit search operation is shown in figure 24, page 41. the entire table consisting of 72-bit entries is compared to a 72-bit word k (pre- sented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 72-bit word speci- fiedbytheidenticalvalueinbothevenandodd gmr pairs selected by the gmr index in the com- mand s cycle a. the 72-bit word k (presented on the dq bus in both cycles a and b of the com- mand)isalsostoredinbothevenandoddcom- parand register pairs selected by the comparand register index in the command scycleb.inax72 configuration, only the even comparand register can be subsequently used by the learn com- mand. the word k (presented on the dq bus in both cycles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entry s location address, l, is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see sram addressing, page 128). the search command is a pipelined operation and executes a search at half the rate of the fre- quency of clk2x for 72-bit searches in x72-con- figured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 72-bit search command cycle (two clk2x cycles) is shown in table 26, page 41. the latency of a search from command to sram access cycle is 4 for a single device in the table and tlsz = 00. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 27, page 41. figure 22. hardware diagram for a table with one device dq[71:0] cmdv, cmd[10:0] ssf, ssv sram bhi[2:0] bhi[2:0] lho[1] lhi 3210 m7040 lho[0] 654 ai04677
m7040n 40/159 figure 23. 72-bit configuration search timing diagram for one device cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l ale_l ai04676 a b a b a b a b dq d1 d2 d3 a1 a3 d4 search3 hit search4 miss search1 hit search2 miss cfg = 0000000000000000, hlat = 000, tlsz = 00, lram = 1, ldev = 1 search1 search2 search3 search4 01 01 01 01 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0
41/159 m7040n figure 24. x72 table with one device table 26. latency of search from instruction to sram access cycle, 72-bit table 27. shift of ssf and ssv from sadr # of devices max table size latency in clk cycles 1 (tlsz = 00) 64k x 72-bit 4 2 C 8 (tlsz = 01) 512k x 72-bit 5 2 C 31 (tlsz = 10) 1984k x 72-bit 6 comparand register (even) comparand register (odd) 71 0 k cfg = 0000000000000000 0 1 2 3 65535 (288-bit configuration) location address l k comparand register (even) 71 0 k gmr 71 0 ai04678 (first matching entry) hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
m7040n 42/159 72-bit search on tables configured as x72 using up to eight m7040n devices the hardware diagram of the search subsystem of eight devices is shown in figure 25, page 43. the following are the parameters programmed into the eight devices: C first seven devices (device 0 C 6): cfg = 0000000000000000, tlsz = 01, hlat = 010, lram = 0, and ldev = 0. C eighth device (device 7): cfg = 0000000000000000, tlsz = 01, hlat = 010, lram = 1, and ldev = 1. note: all eight devices must be programmed with the same values for tlsz and hlat. only the last device in the table (device 7 in this case) must be programmed with lram = 1 and ldev = 1. all other upstream devices (devices 0 through 6 in this case) must be programmed with lram = 0 and ldev = 0. figure 27, page 45 shows the timing diagram for a search command in the 72-bit-configured table of eight devices for device 0. figure 28, page 46 shows the timing diagram for a search com- mand in the 72-bit-configured table of eight devic- es for device 1. figure 29, page 47 shows the timing diagram for a search command in the 72-bit-configured table of eight devices for device 7 (the last device in this specific table). for these timing diagrams four 72-bit searches are per- formed sequentially. hit/miss assumptions were made as shown below in table 28. the sequence of operation for a 72-bit search command is as follows:] C cycle a: thehostasicdrivescmdvhighand applies the search command code ('10') on cmd[1:0] signals. {cmd[10], cmd[5:3] must be driven with the index to the global mask register pair for use in the search operation. cmd[8:6] signals must be driven with the same bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven with the 72- bit data to be compared. the cmd[2] signal must be driven to logic '0.' C cycle b: the host asic continues to drive cmdv high and applies the search command ('10') on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for stor- ing the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching en- try and the hit flag (see search-successful registers (ssr[0:7]), page 24). the dq[71:0] continues to carry the 72-bit data to be com- pared. note: for 72-bit searches, the host asic must supply the same data on dq[71:0] during both cycles a and b. the even and odd pair of gmrs selected for the comparison must be pro- grammed with the same value. the logical 72-bit search operation is shown in figure 26, page 44. the entire table with eight de- vices of 72-bit entries is compared to a 72-bit word k (presented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 72-bit word specified by the identical value in both even and odd gmr pairs in each of the eight devices and selected by the gmr index in the command scy- cle a. the 72-bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs (selected by the comparand register index in command cycle b) in each of the eight devices. in the x72 configuration, only the even comparand register can subsequently be used by the learn command in one of the devices (only the first non- full device). the word k (presented on the dq bus in both cycles a and b of the command) is com- pared with each entry in the table starting at loca- tion 0. the first matching entry s location address, l, is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see sram addressing, page 128). the global winning device will drive the bus in a specif- ic cycle. on a global miss cycle the device with lram = 1 (default driving device for the sram bus) and ldev = 1 (default driving device for ssf and ssv signals) will be the default driver for such missed cycles. the search command is a pipelined operation and executes a search at half the rate of the fre- quency of clk2x for 72-bit searches in x72-con- figured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 72-bit search command cycle (two clk2x cycles) is shown in table 29, page 48 the latency of the search from command to sram access cycle is 5 for up to eight devices in the table (tlsz = 01). ssv and ssf also shift further to the right for different values of hlat, as specified in table 30, page 48.
43/159 m7040n table 28. hit/miss assumption figure 25. hardware diagram for a table with eight devices search number 1 2 3 4 device 0 hit miss hit hit device 1 miss hit hit miss device 2-6 miss miss miss miss device 7 miss miss hit hit sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7040 #0 m7040 #1 m7040 #2 m7040 #3 m7040 #4 m7040 #5 m7040 #6 m7040 #7 lho[0] 654 654 654 654 654 654 654 654 ai04679 ssf, ssv dq[71:0] cmdv cmd[10:0]
m7040n 44/159 figure 26. x72 table with eight devices comparand register (even) comparand register (odd) 71 0 k cfg = 0000000000000000 0 1 2 3 524287 (72-bit configuration) location address l k must be the same in each of the eight devices will be the same in each of the eight devices 71 0 k gmr 71 0 ai04683 (first matching entry)
45/159 m7040n timing diagrams for x72 using up to eight m7040n devices figure 27. timing diagram for 72-bit search for device 0 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04680 a b a b a b a b dq d1 d2 d3 a1 a3 d4 (lhi[6:0]) (1) search3 (this device is the global winner.) search4 (miss on this device.) search1 (this device is the global winner.) search2 (miss on this device.) cfg = 0000000000000000, hlat = 010, tlsz = 01, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 z z z z z 0 0 z z 1 1 z z 0 0 z z 1 1 1 z 1 z z z zz
m7040n 46/159 figure 28. timing diagram for 72-bit search for device 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04681 a b a b a b a b dq d1 d2 d3 a2 d4 (lhi[6:0]) (1) search3 (local winner but not global winner.) search4 (miss on this device.) search1 (miss on this device.) search2 (this device is global winner.) cfg = 0000000000000000, hlat = 010, tlsz = 01, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z z z z z 0 z 1 z 0 z 1 1 z z z
47/159 m7040n figure 29. timing diagram for 72-bit search for device 7 (last device) note: 1. |(lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04682 a b a b a b a b dq d1 d2 d3 a2 d4 |(lhi[6:0]) (1) search3 (local winner but not global winner.) search4 (global winner.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0000000000000000, hlat = 010, tlsz = 01, lram = 1, ldev = 1 search1 search2 search3 search4 01 01 01 01 0 0 z 0 1 0 z 0 0 0 z 1 z 1 z z 1 0 0
m7040n 48/159 table 29. latency of search from instruction to sram access cycle table 30. shift of ssf and ssv from sadr 72-bit search on tables configured as x72 using up to 31 m7040n devices the hardware diagram of the search subsystem of 31 devices is shown in figure 30, page 50. each of the four blocks in the diagram represents eight m7040n devices (except the last, which has seven devices). the diagram for a block of eight devices is shown in figure 31, page 51. the following are the parameters programmed into the 31 devices: C first thirty devices (devices 0 C 29): cfg = 0000000000000000, tlsz = 10, hlat = 001, lram = 0, and ldev = 0. C thirty-first device (device 30): cfg = 0000000000000000, tlsz = 10, hlat = 001, lram = 1, and ldev = 1. note: all 31 devices must be programmed with the same values for tlsz and hlat. only the last de- vice in the table must be programmed with lram = 1 and ldev = 1 (device 30 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 29 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 31, page 49. for the purpose of illustrating the timings, it is further assumed that there is only one device with a matching entry in each of the blocks. figure 33, page 53 shows the timing dia- gram for a search command in the 72-bit-con- figured table of 31 devices for each of the eight devices in block number 0. figure 34, page 54 shows a timing diagram for a search command in the 72-bit-configured table of 31 devices for the all the devices in block number 1 (above the win- ning device in that block). figure 35, page 55 shows the timing diagram for the globally winning device (defined as the final winner within its own and all blocks) in block number 1. figure 36, page 56 shows the timing diagram for all the devices be- low the globally winning device in block number 1. figure 37, page 57, figure 38, page 58, and fig- ure 39, page 59 show the timing diagrams of the devices above the globally winning device, the glo- bally winning device, and the devices below the globally winning device, respectively, for block number 2. figure 40, page 60, figure 41, page 61, figure 42, page 62, and figure 43, page 63 show the timing diagrams of the devices above globally winning device, the globally winning device, and the devices below the globally winning device ex- cept the last device (device 30), respectively, for block number 3. # of devices max table size latency in clk cycles 1 (tlsz = 00) 64k x 72-bit 4 1 C 8 (tlsz = 01) 512k x 72-bit 5 1 C 31 (tlsz = 10) 1984k x 72-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
49/159 m7040n the following is the sequence of operation for a single 72-bit search command (also refer to command codes, page 30). C cycle a: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:6] signals must be driven with the same bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven with the 72- bit data to be compared. the cmd[2] signal must be driven to a logic '0.' C cycle b: the host asic continues to drive the cmdv high and applies search command ('10') on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for stor- ing the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching en- try and the hit flag (see search-successful registers (ssr[0:7]), page 24). the dq[71:0] continues to carry the 72-bit data to be com- pared. note: for 72-bit searches, the host asic must supply the same 72-bit data on dq[71:0] during both cycles a and b. the even and odd pair of gmrs selected for the comparison must be pro- grammed with the same value. the logical 72-bit search operation is shown in figure 32, page 52. the entire table (31 devices of 72-bit entries) is compared to a 72-bit word k (pre- sented on the dq bus in both cycles a and b of the command) using the gmr and the local mask bits. the effective gmr is the 72-bit word speci- fiedbytheidenticalvalueinbothevenandodd gmr pairs in each of the eight devices and select- ed by the gmr index in the command s cycle a. the 72-bit word k (presented on the dq bus in both cycles a and b of the command) is also stored in both even and odd comparand register pairs in each of the eight devices and selected by the comparand register index in command scy- cle b. in the x72 configuration, the even com- parand register can be subsequently used by the learn command only in the first non-full device. the word k (presented on the dq bus in both cy- cles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entry s location address, l, is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see sram ad- dressing, page 128). the global winning device will drive the bus in a specific cycle. on global miss cycles the device with lram = 1 and ldev = 1 will be the default driver for such missed cycles. the search command is a pipelined operation and executes a search at half the rate of the fre- quency of clk2x for 72-bit searches in x72-con- figured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 72-bit search command cycle (two clk2x cycles) is shown in table 32, page 64. forupto31devicesinthetable(tlsz=10), search latency from command to sram access cycle is 6. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 33, page 64. the 72-bit search operation is pipelined and ex- ecutes as follows: C four cycles from the search command, each of the devices knows the outcome internal to it for that operation; C in the fifth cycle after the search command, the devices in a block arbitrate for a winner amongst them (a block being defined as less than or equal to eight devices resolving the win- ner within them using the lhi[6:0] and lho[1:0] signalling mechanism); C in the sixth cycle after the search command, the blocks (of devices) resolve the winning block through the bhi[2:0] and bho[2:0] signalling mechanism. the winning device within the win- ning block is the global winning device for a search operation. table 31. hit/miss assumption search number 1 2 3 4 block 0 miss miss miss miss block 1 miss miss hit miss block 2 miss hit hit miss block 3 hit hit miss miss
m7040n 50/159 figure 30. hardware diagram for a table with 31 devices sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block of 8 m7040s, block 0 (devices 0-7) block of 8 m7040s, block 1 (devices 8-15) block of 8 m7040s, block 2 (devices 16-23) block of 7 m7040s, block 3 (devices 24-30) ai04684 gnd gnd gnd ssf, ssv cmd[10:0], cmdv dq[71:0]
51/159 m7040n figure 31. hardware diagram for a block of up to eight devices dq[71:0] sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7040 #0 m7040 #1 m7040 #2 m7040 #3 m7040 #4 m7040 #5 m7040 #6 m7040 #7 lho[0] 654 654 654 654 654 654 654 654 ai04685 cmdv cmd[10:0] ssv, ssf
m7040n 52/159 figure 32. x72 table with 31 devices comparand register (even) comparand register (odd) 71 0 k cfg = 0000000000000000 0 1 2 3 2031615 (72-bit configuration) location address l k must be the same for each of the 31 devices will be the same in each of the 31 devices 71 0 k gmr 71 0 ai04696 (first matching entry)
53/159 m7040n timing diagrams for x72 using up to 31 m7040n devices figure 33. timing diagram for each device in block number 0 (miss on each device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04686 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z 0 0 0 0 z z z z z z
m7040n 54/159 figure 34. timing diagram for each device above the winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04686 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z 0 0 0 0 z z z z z z
55/159 m7040n figure 35. timing diagram for the globally winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04687 a b a b a b a b dq d1 d2 d3 a3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (this device global winner.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z z z z z 0 0 1 z z
m7040n 56/159 figure 36. timing diagram for devices below the winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04688 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
57/159 m7040n figure 37. timing diagram for devices above the winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04689 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
m7040n 58/159 figure 38. timing diagram for the globally winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04690 a b a b a b a b dq d1 d2 d3 a2 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (hit but not a winner.) search4 (miss on this device.) search1 (miss on this device.) search2 (global winner.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 1 1 1 0 0 0 z z z z z z z z z z z
59/159 m7040n figure 39. timing diagram for devices below the winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04691 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
m7040n 60/159 figure 40. timing diagram for devices above the winning device in block number 3 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04692 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
61/159 m7040n figure 41. timing diagram for the globally winning device in block number 3 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04693 a b a b a b a b dq d1 d2 d3 a1 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (global winner.) search2 (hit but not a global winner.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 1 1 1 0 0 0 z z z z z z z z z z z
m7040n 62/159 figure 42. timing diagram for devices below the winning device in block number 3 (except device 30 - the last device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04694 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
63/159 m7040n figure 43. timing diagram for device 6 in block number 3 (device 30 in depth-cascaded table) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04695 a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (hit on some device above.) search4 (global miss; this device default driver.) search1 (hit on some device above.) search2 (hit on some device above.) cfg = 0000000000000000, hlat = 001, tlsz = 10, lram = 1, ldev = 1 search1 search2 search3 search4 01 01 01 01 0 0 z z z z z 0 0 0 0 z 0 1 0 0 0 1 1 0 0
m7040n 64/159 table 32. latency of search from instruction to sram access cycle table 33. shift of ssf and ssv from sadr 144-bit configuration with single device the hardware diagram for this search subsystem is shown in figure 44. figure 45, page 66 shows the timing diagram for a search command in the 144-bit-configured ta- ble (cfg = 0101010101010101) consisting of a single device for one set of parameters. this illus- tration assumes that the host asic has pro- grammed tlsz to '00,' hlat to '001,' lram to '1,' and ldev to '1.' the following is the operation sequence for a sin- gle 144-bit search command (refer to com- mand codes and parameters, page 30). C cycle a: the host asic drives the cmdv high and applies search command code ('10') to cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:6] signals must be driven with the same bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven with the 72- bit data ([143:72]) to be compared against all even locations. the cmd[2] signal must be driv- en to logic '0.' C cycle b: the host asic continues to drive the cmdv high and applies the command code of search command ('10') on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and hit flag (see search-successful registers (ssr[0:7]), page 24). the dq[71:0] is driven with 72-bit data ([71:0]), compared to all odd locations. note: for 144-bit searches, the host asic must supply two distinct 72-bit data words on dq[71:0] during cycles a and b. the even- numbered gmr of the pair specified by the gmr index is used for masking the word in cy- cle a. the odd-numbered gmr of the pair spec- ified by the gmr index is used for masking the word in cycle b. # of devices max table size latency in clk cycles 1 (tlsz = 00) 64k x 72-bit 4 1 C 8 (tlsz = 01) 512k x 72-bit 5 1 C 31 (tlsz = 10) 1984k x 72-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
65/159 m7040n the logical 144-bit search operation is shown in figure 46, page 67. the entire table of 144-bit en- tries is compared to a 144-bit word k (presented on the dq bus in cycles a and b of the command) using the gmr and the local mask bits. the gmr is the 144-bit word specified by the even and odd global mask pair selected by the gmr index in the command s cycle a. the 144-bit word k (present- ed on the dq bus in cycles a and b of the com- mand) is also stored in both even and odd comparand register pairs selected by the com- parand register index in the command s cycle b. the two comparand registers can subsequently be used by the learn command with the even comparand register stored in an even location, and the odd comparand register stored in an adja- cent odd location. the word k (presented on the dq bus in cycles a and b of the command) is compared with each entry in the table starting at location 0. the first matching entry s location ad- dress, l, is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see sram addressing, page 128). note: the matching address is always going to an even address for a 144-bit search. the search command is a pipelined operation that executes searches at half the rate of the fre- quency of clk2x for 144-bit searches in x144- configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 144-bit search command cycle (two clk2x cycles) is shown in table 34, page 67. for a single device in the table with tlsz = 00, the latency of the search from command to sram access cycle is 4. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 35, page 67. figure 44. hardware diagram for a table with 1 device dq[71:0] cmdv, cmd[10:0] ssf, ssv sram bhi[2:0] bho[2:0] lho[1] lhi 3210 m7040 lho[0] 654 ai04698
m7040n 66/159 figure 45. timing diagram for a 144-bit search for 1 device cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l ale_l ai04697 a b a b a b a b a b a b a b a b dq d1 d2 d3 a1 a3 d4 search3 hit search4 miss search1 hit search2 miss cfg = 0101010101010101, hlat = 001, tlsz = 00, lram = 1, ldev = 1 search1 search2 search3 search4 01 01 01 01 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0
67/159 m7040n figure 46. x144 table with one device table 34. latency of search from instruction to sram access cycle, 144-bit table 35. shift of ssf and ssv from sadr # of devices max table size latency in clk cycles 1 (tlsz = 00) 32k x 144-bit 4 1 C 8 (tlsz = 01) 256k x 144-bit 5 1 C 31 (tlsz = 10) 992k x 144-bit 6 comparand register (even) comparand register (odd) 71 0 a cfg = 0101010101010101 0 1 2 3 32766 (144-bit configuration) location address l b 143 0 k gmr 143 0 ai04699 (first matching entry) even odd b a hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
m7040n 68/159 144-bit search on tables configured as x144 using up to eight m7040n devices the hardware diagram of the search subsystem of eight devices is shown in figure 47, page 69. the following are parameters programmed into the eight devices: C first seven devices (devices 0 C 6): cfg = 0101010101010101, tlsz = 01, hlat = 010, lram = 0, and ldev = 0. C eighth device (device 7): cfg = 0101010101010101, tlsz = 01, hlat = 010, lram = 1, and ldev = 1. note: all eight devices must be programmed with the same value of tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device 7 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 6 in this case). figure 49, page 71 shows the timing diagram for a search command in the 144-bit-configured ta- ble of eight devices for device 0. figure 50, page 72 shows the timing diagram for a search com- mand in the 144-bit-configured table consisting of eight devices for device 1. figure 51, page 73 shows the timing diagram for a search com- mand in the 144-bit configured table consisting of eight devices for device 7 (the last device in this specific table). for these timing diagrams, four 144-bit searches are performed sequentially, and the following hit/miss assumptions were made (see table 36) the following is the sequence of operation for a single 144-bit search command (see com- mand codes and parameters, page 30). C cycle a: thehostasicdrivescmdvhighand applies search command code ('10') on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:6] signals must be driven with the same bits that will be driven by this device on sadr[23:21] if it has a hit. dq[71:0] must be driven with the 72- bit data ([143:72]) in order to be compared against all even locations. the cmd[2] signal must be driven to a logic '0.' C cycle b: the host asic continues to drive cmdv high and to apply the command code for search command ('10') on cmd[1:0]. cmd[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the ssr index that will be used for storing the ad- dress of the matching entry and the hit flag (see search-successful registers (ssr[0:7]), page 24). the dq[71:0] is driven with 72-bit data ([71:0]) compared against all odd locations. the logical 144-bit search operation is shown in figure 48, page 70. the entire table (eight devices of 144-bit entries) is compared to a 144-bit word k (presented on the dq bus in cycles a and b of the command) using the gmr and local mask bits. the gmr is the 144-bit word specified by the even and odd global mask pair selected by the gmr in- dex in the command s cycle a. the 144-bit word k (presented on the dq bus in cycles a and b of the command) is also stored in the even and odd comparand registers specified by the comparand register index in the com- mand s cycle b. in x144 configurations, the even and odd comparand registers can subsequently be used by the learn command in only one of the devices (the first non-full device). the word k (presented on the dq bus in cycles a and b of the command) is compared to each entry in the table starting at location 0. the first matching entry s location, l, is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see sram addressing, page 128). the global winning device will drive the bus in a specif- ic cycle. on global miss cycles the device with lram = 1 (the default driving device for the sram bus) and ldev = 1 (the default driving device for ssf and ssv signals) will be the default driver for such missed cycles. note: during 144-bit searches of 144-bit-config- ured tables, the search hit will always be at an even address. the search command is a pipelined operation and executes a search at half the rate of the fre- quency of clk2x for 144-bit searches in x144- configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 144-bit search command cycle (two clk2x cycles) is shown in table 37, page 74. for one to eight devices in the table and tlsz = 01, the latency of a search from com- mand to sram access cycle is 5. in addition, ssv and ssf shift further to the right for different val- ues of hlat as specified in table 38, page 74.
69/159 m7040n table 36. hit/miss assumption figure 47. hardware diagram for a table with eight devices search number 1 2 3 4 device 0 hit miss hit miss device 1 miss hit hit miss device 2-6 miss miss miss miss device 7 miss miss hit hit sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7040 #0 m7040 #1 m7040 #2 m7040 #3 m7040 #4 m7040 #5 m7040 #6 m7040 #7 lho[0] 654 654 654 654 654 654 654 654 ai04679 ssf, ssv dq[71:0] cmdv cmd[10:0]
m7040n 70/159 figure 48. x144 table with eight devices comparand register (even) comparand register (odd) 71 0 a cfg = 0101010101010101 0 1 2 3 262142 (144-bit configuration) location address l b 143 0 k gmr 143 0 ai04701 (first matching entry) even odd b a must be the same in each of the eight devices will be the same in each of the eight devices
71/159 m7040n timing diagrams for x144 using up to eight m7040n devices figure 49. timing diagram for 144-bit search for device number 0 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04664 a b a b a b a b a b a b a b a b dq d1 d2 d3 a1 a3 d4 (lhi[6:0]) (1) search3 (this device is the global winner.) search4 (miss on this device.) search1 (this device is the global winner.) search2 (miss on this device.) cfg = 0101010101010101, hlat = 010, tlsz = 01, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 z z z z z 0 0 z z 1 1 z z 0 0 z z 1 1 1 z 1 z z z zz
m7040n 72/159 figure 50. timing diagram for 144-bit search for device number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04663 a b a b a b a b a b a b a b a b dq d1 d2 d3 a2 d4 (lhi[6:0]) (1) search3 (local winner but not global winner.) search4 (miss on this device.) search1 (miss on this device.) search2 (this device is global winner.) cfg = 0000000000000000, hlat = 010, tlsz = 01, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z z z z z 0 z 1 z 0 z 1 1 z z z
73/159 m7040n figure 51. timing diagram for 144-bit search for device number 7 (last device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04700 a b a b a b a b a b a b a b a b dq d1 d2 d3 a4 d4 (lhi[6:0]) (1) search3 (local winner but not global winner.) search4 (global winner.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0101010101010101, hlat = 010, tlsz = 01, lram = 1, ldev = 1 search1 search2 search3 search4 01 01 01 01 0 0 z 0 1 0 z 0 0 0 z 1 z 1 z z 1 0 0
m7040n 74/159 table 37. latency of search from instruction to sram access cycle, 144-bit table 38. shift of ssf and ssv from sadr 144-bit search on tables configured as x144 using up to 31 m7040n devices the hardware diagram of the search subsystem of 31 devices is shown in figure 52, page 76. each of the four blocks in the diagram represents a block of eight m7040n devices (except the last, which has seven devices).the diagram for a block of eight devices is shown in figure 53, page 77. following are the parameters programmed into the 31 devices. first thirty devices (devices 0 C 29): cfg = 0101010101010101, tlsz = 10, hlat = 001, lram = 0, and ldev = 0. thirty-first device (device 30): cfg = 0101010101010101, tlsz = 10, hlat = 001, lram = 1, and ldev = 1. note: all 31 devices must be programmed with the same value of tlsz and hlat. only the last de- vice in the table must be programmed with lram = 1 and ldev = 1 (device 30 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 29 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 39, page 75. for the purpose of illustrating timings, it is further assumed that the there is only one device with a matching entry in each of the blocks. figure 55, page 79 shows the timing dia- gram for a search command in the 144-bit-con- figured table (31 devices) for each of the eight devices in block 0. figure 56, page 80 shows the timing diagram for search command in the 72-bit-configured table (31 devices) for all the de- vices in block 1 above the winning device in that block. figure 57, page 81 shows the timing dia- gram for the globally winning device (the final win- ner within its own block and all blocks) in block 1. figure 58, page 82 shows the timing diagram for all the devices below the globally winning device in block 1. figure 59, page 83, figure 60, page 84, and figure 61, page 85 respectively show the tim- ing diagrams of the devices above globally win- ning device, the globally winning device and devices below the globally winning device for block 2. figure 62, page 86, figure 63, page 87, figure 64, page 88, and figure 65, page 89 re- spectively show the timing diagrams of the devices above the globally winning device, the globally winning device, and devices below the globally winning device except the last device (device 30), and the last device (device 30) for block 3. # of devices max table size latency in clk cycles 1 (tlsz = 00) 32k x 144-bit 4 1 C 8 (tlsz = 01) 256k x 144-bit 5 1 C 31 (tlsz = 10) 992k x 144-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
75/159 m7040n the following is the sequence of operation for a single 144-bit search command (see com- mand codes and parameters, page 30). C cycle a: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair for use in this search operation. cmd[8:6] signals must be driven with the bits that will be driven on sadr[23:21] by this device if it has a hit. dq[71:0] must be driven with the 72-bit data ([143:72]) in order to be compared against all even locations. the cmd[2] signal must be driv- en to logic '0.' C cycle b: the host asic continues to drive the cmdv high and to apply search command code ('10') on cmd[1:0]. cmd[5:2] must be driv- en by the index of the comparand register pair for storing the 144-bit word presented on the dq bus during cycles a and b. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see search- successful registers (ssr[0:7]), page 24). the dq[71:0] is driven with 72-bit data ([71:0]) to be compared against all odd locations. the logical 144-bit search operation is as shown in figure 54, page 78. the entire table of 31 devices (consisting of 144-bit entries) is compared against a 144-bit word k that is presented on the dq bus in cycles a and b of the command using the gmr and local mask bits. the gmr is the 144-bit word specified by the even and odd global mask pair se- lected by the gmr index in the command s cycle a. the 144-bit word k that is presented on the dq busincyclesaandbofthecommandisalso stored in the even and odd comparand registers specified by the comparand register index in the command s cycle b. in x144 configurations, the even and odd comparand registers can subse- quently be used by the learn command in only the first non-full device. note: the learn command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than one block. the word k that is presented on the dq bus in cy- cles a and b of the command is compared with each entry in the table starting at location 0. the first matching entry s location address, l, is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see sram ad- dressing, page 128). the global winning device will drive the bus in a specific cycle. on global miss cyclesthedevicewithlram=1(thedefaultdriv- ing device for the sram bus) and ldev = 1 (the default driving device for ssf and ssv signals) will be the default driver for such missed cycles. note: during 144-bit searches of 144-bit-config- ured tables, the search hit will always be at an even address. the search command is a pipelined operation. it executes a search at half the rate of the frequen- cy of clk2x for 144-bit searches in x144-config- ured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 144-bit search command cycle (two clk2x cycles) is shown in table 40, page 90. the latency of a search from command to the sram access cycle is 6 for 1 C 31 devices in the ta- ble and where tlsz = 10. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 41, page 90. the 144-bit search operation is pipelined and executes as follows: C four cycles from the search command, each of the devices knows the outcome internal to it for that operation. C in the fifth cycle after the search command, the devices in a block (being less than or equal to eight devices resolving the winner within them using the lhi[6:0] and lho[1:0] signalling mechanism) arbitrate for a winner amongst them. C in the sixth cycle after the search command, the blocks (of devices) resolve the winning block through the bhi[2:0] and bho[2:0] signalling mechanism. the winning device in the winning block is the global winning device for a search operation. table 39. hit/miss assumption search number 1 2 3 4 block 0 miss miss miss miss block 1 miss miss hit miss block 2 miss hit hit miss block 3 hit hit miss miss
m7040n 76/159 figure 52. hardware diagram for a table with 31 devices sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block of 8 m7040s, block 0 (devices 0-7) block of 8 m7040s, block 1 (devices 8-15) block of 8 m7040s, block 2 (devices 16-23) block of 7 m7040s, block 3 (devices 24-30) ai04684 gnd gnd gnd ssf, ssv cmd[10:0], cmdv dq[71:0]
77/159 m7040n figure 53. hardware diagram for a block of up to eight devices dq[71:0] sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7040 #0 m7040 #1 m7040 #2 m7040 #3 m7040 #4 m7040 #5 m7040 #6 m7040 #7 lho[0] 654 654 654 654 654 654 654 654 ai04685 cmdv cmd[10:0] ssv, ssf
m7040n 78/159 figure 54. x144 table with 31 devices comparand register (even) comparand register (odd) 71 0 a cfg = 0101010101010101 0 1 2 3 1015806 (144-bit configuration) location address l b 143 0 k gmr 143 0 ai04702 (first matching entry) even odd b a must be the same in each of the 31 devices will be the same in each of the 31 devices
79/159 m7040n timing diagrams for x144 using up to 31 m7040n devices figure 55. timing diagram for each device in block number 0 (miss on each device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04703 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z 0 0 0 0 z z z z z z
m7040n 80/159 figure 56. timing diagram for each device above the winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04703 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) bho[2:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z 0 0 0 0 z z z z z z
81/159 m7040n figure 57. timing diagram for the globally winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04704 a b a b a b a b a b a b a b a b dq d1 d2 d3 a3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (this device global winner.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 1 1 1 0 0 0 z z z z z z z z z z z
m7040n 82/159 figure 58. timing diagram for devices below the winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04705 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
83/159 m7040n figure 59. timing diagram for devices above the winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04706 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
m7040n 84/159 figure 60. timing diagram for the globally winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04707 a b a b a b a b a b a b a b a b dq d1 d2 d3 a2 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (hit but not a winner.) search4 (miss on this device.) search1 (miss on this device.) search2 (global winner.) cfg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 1 1 1 0 0 0 z z z z z z z z z z z
85/159 m7040n figure 61. timing diagram for devices below the winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04708 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
m7040n 86/159 figure 62. timing diagram for devices above the winning device in block number 3 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04709 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
87/159 m7040n figure 63. timing diagram for the globally winning device in block number 3 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04710 a b a b a b a b a b a b a b a b dq d1 d2 d3 a1 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (global winner.) search2 (hit but not a global winner.) cfg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 1 1 1 0 0 0 z z z z z z z z z z z
m7040n 88/159 figure 64. timing diagram for devices below the winning device in block number 3 (except device 30 - the last device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04711 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (miss on this device.) search4 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 0101010101010101, hlat = 001, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 search4 01 01 01 01 z z 0 0 0 0 z z z z z
89/159 m7040n figure 65. timing diagram for device 6 in block number 3 (device 30 in depth-cascaded table) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) bho[2:0] (4) ale_l ai04712 a b a b a b a b a b a b a b a b dq d1 d2 d3 d4 (lhi[6:0]) (1) (bhi[2:0]) (3) search3 (hit on some device above.) search4 (global miss; this device default driver.) search1 (hit on some device above.) search2 (hit on some device above.) cfg = 0101010101010101, hlat = 001, tlsz = 10, lram = 1, ldev = 1 search1 search2 search3 search4 01 01 01 01 0 0 z z z z z 0 0 0 0 z 0 1 0 0 0 1 1 0 0
m7040n 90/159 table 40. latency of search from instruction to sram access cycle, 144-bit table 41. shift of ssf and ssv from sadr 288-bit search on tables configured as x288 using a single m7040n device the hardware diagram for this search subsystem is shown in figure 66, page 91. figure 67, page 92 shows the timing diagram for a search com- mand in the 288-bit-configured table (cfg = 1010101010101010) consisting of a single device for one set of parameters: tlsz = '00,' hlat = '001,' lram = '1,' and ldev = '1.' the following is the sequence of operation for a single 144-bit search command (also refer to command codes and parameters, page 30). C cycle a: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [287:144] of the data being searched. dq[71:0] must be driven with the 72- bit data ([287:216]) to be compared to all loca- tions 0 in the four 72-bits-word page. the cmd[2] signal must be driven to logic 1. note: cmd[2] = 1 signals that the search is a x288-bit search. cmd[8:3] in this cycle is ig- nored. C cycle b: the host asic continues to drive the cmdv high and continues to apply the com- mand code of search command ('10') on cmd[1:0]. the dq[71:0] is driven with the 72-bit data ([215:144]) to be compared to all locations 1 in the four 72-bits-word page. C cycle c: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [143:0] of the data being searched. cmd[8:6] signals must be driven with the bits that will be driven on sadr[23:21] by this de- vice if it has a hit. dq[71:0] must be driven with the 72-bit data ([143:72]) to be compared to all locations 2 in the four 72-bits-word page. the cmd[2] signal must be driven to logic '0.' C cycle d: the host asic continues to drive the cmdv high and applies search command code ('10') on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching en- try and the hit flag (see search-successful registers (ssr[0:7]), page 24). the dq[71:0] is driven with the 72-bit data ([71:0]) to be com- pared to all locations 3 in the four 72-bits-word page. cmd[5:2] is ignored because the learn instruction is not supported for x288 tables. note: for 288-bit searches, the host asic must supply four distinct 72-bit data words on dq[71:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs that apply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs that apply to dq data in cycles c and d. # of devices max table size latency in clk cycles 1 (tlsz = 00) 32k x 144-bit 4 1 C 8 (tlsz = 01) 256k x 144-bit 5 1 C 31 (tlsz = 10) 992k x 144-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
91/159 m7040n the logical 288-bit search operation is shown in figure 68, page 93. the entire table of 288-bit en- tries is compared to a 288-bit word k that is pre- sented on the dq bus in cycles a, b, c, and d of the command using the gmr and local mask bits. the gmr is the 288-bit word specified by the two pairs of gmrs selected by the gmr indexes in the command scyclesaandc.the288-bitwordk that is presented on the dq bus in cycles a, b, c, and d of the command is compared with each en- try in the table starting at location 0. the first matching entry s location address, l, is the win- ning address that is driven as part of the sram address on sadr[23:0] lines (see sram ad- dressing, page 128). note: the matching address is always going to be location 0 in a four-entry page for a 288-bit search (two lsbs of the matching index will be '00'). the search command is a pipelined operation and executes at one-fourth the rate of the frequen- cy of clk2x for 288-bit searches in x288-config- ured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 288-bit search command (measured in clk cycles) from the clk2x cycle that contains the c and d cycles is shown in table 42, page 93. the latency of a search from command to sram access cycle is 4 for only a single device in the table and tlsz = 00. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 43, page 93. figure 66. hardware diagram for a table with one device dq[71:0] cmdv, cmd[10:0] ssf, ssv sram bhi[2:0] bho[2:0] lho[1] lhi 3210 m7040 lho[0] 654 ai04698
m7040n 92/159 figure 67. timing diagram for 288-bit search (one device) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l ale_l ai04713 a b a b a b a b a b c d a b c d dq d1 d2 a1 search1 hit search2 miss cfg = 1010101010101010, hlat = 001, tlsz = 00, lram = 1, ldev = 1 search1 search2 01 01 1 1 1 1 0 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0
93/159 m7040n figure 68. x288 table with one device table 42. latency of search from cycles c and d to sram access cycle table 43. shift of ssf and ssv from sadr # of devices max table size latency in clk cycles 1 (tlsz = 00) 16k x 288-bit 4 2 C 8 (tlsz = 01) 128k x 288-bit 5 2 C 31 (tlsz = 10) 496k x 288-bit 6 cfg = 1010101010101010 0 4 8 12 16380 (288-bit configuration) location address l 287 0 k gmr 287 0 ai04714 (first matching entry) 0 123 bcd a hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
m7040n 94/159 288-bit search on tables x288-configured using up to eight m7040n devices the hardware diagram of the search subsystem of eight devices is shown in figure 69, page 96. the following are the parameters programmed in the eight devices. C first seven devices (devices 0 C 6): cfg = 1010101010101010, tlsz = 01, hlat = 000, lram = 0, and ldev = 0. C eighth device (device 7): cfg = 1010101010101010, tlsz = 01, hlat = 000, lram = 1, and ldev = 1. note: all eight devices must be programmed with the same value of tlsz and hlat. only the last device in the table must be programmed with lram = 1 and ldev = 1 (device 7 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 6 in this case). figure 71, page 98 shows the timing diagram for a search command in the 288-bit-configured ta- ble of eight devices for device 0. figure 72, page 99 shows the timing diagram for a search com- mand in the 288-bit-configured table of eight de- vices for device 1. figure 73, page 100 shows the timing diagram for a search command in the 288-bit-configured table of eight devices for de- vice 7 (the last device in this specific table). for these timing diagrams three 288-bit searches are performed sequentially. the following hit/miss assumptions were made as shown in table 44, page 95. the following is the sequence of operation for a single 288-bit search command (also com- mand codes and parameters, page 30). C cycle a: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [287:144] of the data being searched in this operation. dq[71:0] must be driven with the 72-bit data ([287:216]) to be compared against all locations 0 in the four- word, 72-bit page. the cmd[2] signal must be driventologic'1.' note: cmd[2] = 1 signals that the search is a 288-bit search. cmd[8:3] in this cycle is ig- nored. C cycle b: the host asic continues to drive the cmdv high and applies search command code ('10') on cmd[1:0]. the dq[71:0] is driven with the 72-bit data ([215:144]) to be compared against all locations 1 in the four 72-bits-word page. C cycle c: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [143:0] of the data being searched. cmd[8:6] signals must be driven with the bits that will be driven on sadr[23:21] by this de- vice if it has a hit. dq[71:0] must be driven with the 72-bit data ([143:72]) to be compared against all locations 2 in the four 72-bits-word page. the cmd[2] signal must be driven to logic '0.' C cycle d: the host asic continues to drive the cmdv high and applies search command code ('10') on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching en- try and the hit flag (see search-successful registers (ssr[0:7]), page 24). the dq[71:0] is driven with the 72-bit data ([71:0]) to be com- pared to all locations 3 in the four 72-bits-word page. cmd[5:2] is ignored because the learn instruction is not supported for x288 tables. note: for 288-bit searches, the host asic must supply four distinct 72-bit data words on dq[71:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs in each of the eight devices that apply to dq data in cycles a and b. the gmr index in cycle c selects a pair of gmrs in each of the eight de- vices that apply to dq data in cycles c and d. the logical 288-bit search operation is shown in figure 70, page 97. the entire table of 288-bit en- tries is compared to a 288-bit word k that is pre- sented on the dq bus in cycles a, b, c, and d of the command using the gmr and the local mask bits. the gmr is the 288-bit word specified by the two pairs of gmrs selected by the gmr indexes in the command s cycles a and c in each of the eight devices. the 288-bit word k that is presented on the dq bus in cycles a, b, c, and d of the com- mand is compared to each entry in the table start- ing at location 0. the first matching entry s location address, l, is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see sram addressing, page 128). note: the matching address is always going to be a location 0 in a four-entry page for 288-bit search (two lsbs of the matching index will be '00').
95/159 m7040n the search command is a pipelined operation and executes search at one-fourth the rate of the frequency of clk2x for 288-bit searches in x288- configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 288-bit search command (measured in clk cycles) from the clk2x cycle that contains the c and d cycles is shown in table 45, page 101. the latency of search from command to sram ac- cess cycle is 5 for only a single device in the table and tlsz = 01. in addition, ssv and ssf shift fur- ther to the right for different values of hlat, as specified in table 46, page 101. table 44. hit/miss assumption search number 1 2 3 device 0 hit miss miss device 1 miss hit miss device 2-6 miss miss miss device 7 miss miss miss
m7040n 96/159 figure 69. hardware diagram for a table with eight devices sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7040 #0 m7040 #1 m7040 #2 m7040 #3 m7040 #4 m7040 #5 m7040 #6 m7040 #7 lho[0] 654 654 654 654 654 654 654 654 ai04679 ssf, ssv dq[71:0] cmdv cmd[10:0]
97/159 m7040n figure 70. x288 table with eight devices cfg = 1010101010101010 0 4 8 12 131068 (288-bit configuration) location address l 287 0 k gmr 287 0 ai04718 (first matching entry) 0 123 bcd a must be the same in each of eight devices
m7040n 98/159 timing diagrams for x288-configured using up to eight m7040n devices figure 71. timing diagram for 288-bit search for device number 0 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04715 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 a1 (lhi[6:0]) (1) search3 (miss on this device.) search1 (this device is the global winner.) search2 (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 01, lram = 0, ldev = 0 search1 search2 search3 01 01 01 z z 0 z z z z 0 z 1 z 0 z 1 1 z z z z z
99/159 m7040n figure 72. timing diagram for 288-bit search for device number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04716 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 a2 (lhi[6:0]) (1) search3 (miss on this device.) search1 (miss on this device.) search2 (this device is global winner.) cfg = 1010101010101010, hlat = 000, tlsz = 01, lram = 0, ldev = 0 search1 search2 search3 01 01 01 z z z z z 0 z 1 z 0 z 1 1 z z z z
m7040n 100/159 figure 73. timing diagram for 288-bit search for device number 7 (last device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04717 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 a2 (lhi[6:0]) (1) search3 (global miss.) search1 (miss on this device.) search2 (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 01, lram = 1, ldev = 1 search1 search2 search3 01 01 01 0 0 1 0 0 z z z 0 0 0 z z 0 0 z z 1 1 z z z 0 0
101/159 m7040n table 45. latency of search from cycles c and d to sram access cycle, 288-bit table 46. shift of ssf and ssv from sadr 288-bit search on tables configured as x288 using up to 31 m7040n devices the hardware diagram of the search subsystem of 31 devices is shown in figure 74, page 103. each of the four blocks in the diagram represents a block of eight m7040n devices, except the last which has seven devices.the diagram for a block of eight devices is shown in figure 75, page 104. the following are the parameters programmed into the 31 devices. C first thirty devices (devices 0 C 29): cfg = 1010101010101010, tlsz = 10, hlat = 000, lram = 0, and ldev = 0. C thirty-first device (device 30): cfg = 1010101010101010, tlsz = 10, hlat = 000, lram = 1, and ldev = 1. note: all 31 devices must be programmed with the same value of tlsz and hlat. only the last de- vice in the table must be programmed with lram = 1 and ldev = 1 (device 30 in this case). all other upstream devices must be programmed with lram = 0 and ldev = 0 (devices 0 through 29 in this case). the timing diagrams referred to in this paragraph reference the hit/miss assumptions defined in table 47, page 103. for the purpose of illustrating the timings, it is further assumed that there is only one device with the matching entry in each block. figure 77, page 106 shows the timing diagram for a search command in the 288-bit-configured ta- ble consisting of 31 devices for each of the eight devices in block 0. figure 78, page 107 shows the timing diagram for a search command in the 288-bit-configured table of 31 devices for all devic- es above the winning device in block 1. figure 79, page 108 shows the timing diagram for the global- ly winning device (the final winner within its own and all blocks) in block 1. figure 80, page 109 shows the timing diagram for all the devices below the globally winning device in block 1. figure 81, page 110, figure 82, page 111, and figure 83, page 112, respectively, show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winning device for block 2. figure 84, page 113, figure 85, page 114, figure 86, page 115, and figure 87, page 116, respectively, show the timing diagrams of the device above the glo- bally winning device, the globally winning device, the devices below the globally winning device (ex- cept device 30), and last device (device 30) for block 3. # of devices max table size latency in clk cycles 1 (tlsz = 00) 16k x 288-bit 4 1 C 8 (tlsz = 01) 128k x 288-bit 5 1 C 31 (tlsz = 10) 496k x 288-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
m7040n 102/159 the following is the sequence of operation for a single 288-bit search command (see com- mand codes and parameters, page 30). C cycle a: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair used for bits [287:144] of the data being searched. dq[71:0] must be driven with the 72- bit data ([287:216])to be compared to all loca- tions 0 in the four 72-bit-word page. the cmd[2] signal must be driven to logic '1.' note: cmd[2] = 1 signals that the search is a x288-bit search. cmd[8:6] is ignored in this cy- cle. C cycle b: the host asic continues to drive the cmdv high and applies search command ('10') on cmd[1:0]. the dq[71:0] is driven with the 72-bit data ([215:144]) to be compared to all locations '1' in the four 72-bits-word page. C cycle c: the host asic drives the cmdv high and applies search command code ('10') on cmd[1:0] signals. {cmd[10],cmd[5:3]} signals must be driven with the index to the gmr pair used for the bits [143:0] of the data being searched. cmd[8:6] signals must be driven with the bits that will be driven by this device on sadr[23:21] if it has a hit. dq[71:0] must be driven with the 72-bit data ([143:72]) to be com- pared to all locations 2 in the four 72-bit-word page. the cmd[2] signal must be driven to logic '0.' C cycle d: the host asic continues to drive the cmdv high and continues to apply search command code ('10') on cmd[1:0]. cmd[8:6] signals must be driven with the index of the ssr that will be used for storing the address of the matching entry and the hit flag (see search- successful registers (ssr[0:7]), page 24). the dq[71:0] is driven with the 72-bit data ([71:0]) to be compared to all locations 3 in the four 72- bit-word page. cmd[5:2] is ignored because the learn instruction is not supported for x288 ta- bles. note: for 288-bit searches, the host asic must supply four distinct 72-bit data words on dq[71:0] during cycles a, b, c, and d. the gmr index in cycle a selects a pair of gmrs in each of the 31 devices that apply to dq data in cycles a and b. the gmr index in cycle c se- lects a pair of gmrs in each of the 31 devices that apply to dq data in cycles c and d. the logical 288-bit search operation is as shown in figure 76, page 105. the entire table of 288-bit entries is compared to a 288-bit word k that is presented on the dq bus in cycles a, b, c, and d of the command using the gmr and local mask bits. the gmr is the 288-bit word specified by the two pairs of gmrs selected by the gmr in- dexes in the command s cycles a and c in each of the 31 devices. the 288-bit word k that is pre- sented on the dq bus in cycles a, b, c, and d of the command is compared to each entry in the ta- ble starting at location 0. the first matching en- try s location address, l, is the winning address that is driven as part of the sram address on the sadr[23:0] lines (see sram addressing, page 128). note: the matching address is always going to be location 0 in a four-entry page for 288-bit search (two lsbs of the matching index will be '00'). the search command is a pipelined operation and executes a search at one-fourth the rate of the frequency of clk2x for 288-bit searches in x288- configured tables. the latency of sadr, ce_l, ale_l, we_l, ssv, and ssf from the 288-bit search command (measured in clk cycles) from the clk2x cycle that contains cycles c and d shown in table 48, page 117. the latency of a search from command to sram access cycle is 6 for only a single device in the table and tlsz = 10. in addition, ssv and ssf shift further to the right for different values of hlat, as specified in table 49, page 117 the 288-bit search operation is pipelined and executes as follows: C four cycles from the last cycle of the search command each of the devices knows the out- come internal to it for that operation. C in the fifth cycle from the search command, the devices in a block (which is less than or equal to eight devices resolving the winner with- in them using an lhi[6:0] and lho[1:0] signal- ling mechanism) arbitrate for a winner. C in the sixth cycle after the search command, the blocks of devices resolve the winning block through a bhi[2:0] and bho[2:0] signalling mechanism. the winning device within the win- ning block is the global winning device for the search operation.
103/159 m7040n table 47. hit/miss assumption figure 74. hardware diagram for a table with 31 devices search number 1 2 3 block 0 miss miss miss block 1 miss miss hit block 2 miss hit hit block 3 hit hit miss sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block of 8 m7040s, block 0 (devices 0-7) block of 8 m7040s, block 1 (devices 8-15) block of 8 m7040s, block 2 (devices 16-23) block of 7 m7040s, block 3 (devices 24-30) ai04684 gnd gnd gnd ssf, ssv cmd[10:0], cmdv dq[71:0]
m7040n 104/159 figure 75. hardware diagram for a block of up to eight devices dq[71:0] sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7040 #0 m7040 #1 m7040 #2 m7040 #3 m7040 #4 m7040 #5 m7040 #6 m7040 #7 lho[0] 654 654 654 654 654 654 654 654 ai04685 cmdv cmd[10:0] ssv, ssf
105/159 m7040n figure 76. x288 table with 31 devices cfg = 1010101010101010 0 4 8 12 507900 (288-bit configuration) location address l 287 0 k gmr 287 0 ai04729 (first matching entry) 0 123 bcd a must be the same in each of 31 devices
m7040n 106/159 timing diagrams for x288 using up to 31 m7040n devices figure 77. timing diagram for each device in block number 0 (miss on each device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04719 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[1:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 z z 0 0 0 0 z z z z z
107/159 m7040n figure 78. timing diagram for each device above the winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04719 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[1:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 z z 0 0 0 0 z z z z z
m7040n 108/159 figure 79. timing diagram for the globally winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04720 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 a3 (lhi[6:0]) (1) bho[1:0] (4) (bhi[2:0]) (3) search3 (this device global winner.) search1 (miss on this device.) search2 (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z 0 0 1 1 1 z z
109/159 m7040n figure 80. timing diagram for devices below the winning device in block number 1 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04721 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[1:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z
m7040n 110/159 figure 81. timing diagram for devices above the winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04722 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[1:0] (4) (bhi[2:0]) (3) search3 (miss on this device; hit in block 0 or 1.) search1 (miss on this device.) search2 (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z
111/159 m7040n figure 82. timing diagram for the globally winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04723 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 a2 (lhi[6:0]) (1) bho[1:0] (4) (bhi[2:0]) (3) search3 (hit but not a winner.) search1 (miss on this device.) search2 (global winner.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z z z z z z z z 0 0 1 1 1 z z
m7040n 112/159 figure 83. timing diagram for devices below the winning device in block number 2 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04724 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[1:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z
113/159 m7040n figure 84. timing diagram for devices above the winning device in block number 3 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04725 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[1:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z
m7040n 114/159 figure 85. timing diagram for the globally winning device in block number 3 note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04726 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 a1 (lhi[6:0]) (1) bho[1:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (global winner.) search2 (hit but not a global winner.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z z z z z 0 0 1 1 1 z z
115/159 m7040n figure 86. timing diagram for devices below the winning device in block number 3 (except device 30 - the last device) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04727 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 (lhi[6:0]) (1) bho[1:0] (4) (bhi[2:0]) (3) search3 (miss on this device.) search1 (miss on this device.) search2 (miss on this device.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 0, ldev = 0 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z
m7040n 116/159 figure 87. timing diagram of the last device in block number 3 (device 30 in the table) note: 1. (lhi[6:0]) stands for the boolean 'or' of the entire bus lhi[6:0]. 2. each bit in lho[1:0] is the same logical signal. 3. (bhi[2:0]) stands for the boolean 'or' of the entire bus bhi[2:0]. 4. each bit in bho[2:0] is the same logical signal. cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l lho[1:0] (2) ale_l ai04728 a b a b a b a b a b a b a b c d a b c d a b c d dq d1 d2 d3 |(lhi[6:0]) (1) bho[1:0] (4) |(bhi[2:0]) (3) search3 (hit on some device above.) search1 (hit on some device above.) search2 (hit on some device above.) cfg = 1010101010101010, hlat = 000, tlsz = 10, lram = 1, ldev = 1 search1 search2 search3 01 01 01 0 0 0 0 z z z z z z z z z z z z z z z z z 00 0 0 0 0 0 0 1 1 z z
117/159 m7040n table 48. latency of search from cycles c and d to sram access cycle, 288-bit table 49. shift of ssf and ssv from sadr mixed searches tables configured with different widths using an m7040n with cfg_l low the sample operation shown is for a single device with cfg = 1010010100000000. it contains three tables of x72, x144, and x288 widths. the opera- tion may be generalized to a block of 8 C 31 devices using four blocks; the timing and the pipeline oper- ation is the same as described previously for fixed searches on a table of one-width-size. figure 88, page 118 shows three sequential searches: C a 72-bit search on the table configured as x72; C a 144-bit search on a table configured as x144; and C a 288-bit search on the table configured as x288 bits that each results in a hit. note: the dq[71:70] will be '00' in both of the cy- cles a and b of the x72-bit search (search1). dq[71:70] is '01' in both of the cycles a and b of the x144-bit search (search2). dq[71:70] is '10' in all of the cycles a, b, c, and d of the x288-bit search (search 3). by having table designation bits, the m7040n enables the creation of many ta- bles in a bank of search engines of different widths. figure 89, page 119 shows the sample table. two bits in each 72-bit entry will need to designated as the table number bits. one example choice can be the '00' values for the table configured as x72, '01' values for tables configured as x144, and '10' values for tables configured as x288. for the above explanation, it is further assumed that bits [71:70] for each entry will be designed as these table designation bits. tables configured to different widths using an m7040n with cfg_l high searches on tables of different widths using table designation bits in the data array can be wasteful of these bits. in order to avoid wasting these bits and still support up to three tables of x72, x144, and x288, the cmd[2] and cmd[9] (in cfg_l high mode)incycleaofthecommandcanbeusedas shown in table 50, page 119. # of devices max table size latency in clk cycles 1 (tlsz = 00) 16k x 288-bit 4 2 C 8 (tlsz = 01) 128k x 288-bit 5 2 C 31 (tlsz = 10) 496k x 288-bit 6 hlat number of clk cycles 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
m7040n 118/159 figure 88. timing diagram for mixed search (one device) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[2] ce_l we_l oe_l sadr[23:0] ssv ssf cmd[10:2] phs_ l ale_l ai04730 a b a b a b a b a b a b a b c d dq d1 d2 d3 a3 a2 a1 search3 (x288 hit) search1 (x72 hit) search2 (x144 hit) cfg = 1010101010101010, hlat = 010, tlsz = 00, lram = 1, ldev = 1 search1 search2 search3 01 01 01 1 01 01 1 1 01 01 1 0 1 0 1 0 1 0 11 0 00 0 0
119/159 m7040n figure 89. multi-width configurations example table 50. searches with cfg_l set high lram and ldev description when search engines are cascaded using multiple m7040ns, the sadr, ce_l, and we_l (3-state signals) are all tied together. in order to eliminate external pull-up and pull-downs, one device in a bank is designated as the default driver. for non- search or non-learn cycles (see learn command in the section below) or search cycles with a global miss, the sadr, ce_l, and we_l signals are driven by the device with the lram bit set. note: it is important that only one device in a bank of search engines that are cascaded have this bit set. failure to do so will cause contention on sadr, ce_l, we_l, and can potentially cause damage to the device(s). similarly, when search engines using multiple m7040ns are cascaded, ssf and ssv (also 3- state signals) are tied together. in order to elimi- nate external pull-up and pull-downs, one device in a bank is designated as the default driver. for non-search cycles or search cycles with a global miss the ssf and ssv signals are driven by the device with the ldev bit set. note: it is important that only one device in a bank of search engines that are cascaded together have this bit set. failure to do so will cause conten- tion on ssv and ssf and can potentially cause damage to the device(s). cmd[9] cmd[2] search 0 0 search 72-bit-configured partitions only 1 0 search 144-bit-configured partitions only x 1 cycles a and b for searching 288-bit-configured partitions x 0 cycles c and d for searching 288-bit-configured partitions 32 k 8 k 4 k 72 144 288 cfg = 10 10 01 01 00 00 00 00 ai04731
m7040n 120/159 learn command bit [0] of each 72-bit data location specifies wheth- er an entry in the database is occupied. if all the entries in a device are occupied, the device as- serts fulo signal to inform the downstream de- vices that it is full. the result of this communication between depth- cascaded devices determines the global full signal for the entire table. the full signal in the last device determines the fullness of the depth- cascaded table. in a depth-cascaded table, only a single device will learn the entry through the application of a learn instruction. the determination of which device is going to learn is based on the fuli and fulo sig- nalling between the devices. the first non-full de- vice learns the entry by storing the contents of the specified comparand registers to the location(s) pointed to by nfa. in a x72-configured table the learn command writes a single 72-bit location. in a x144-config- ured table the learn command writes the next even and odd 72-bit locations. in 144-bit mode, bit[0] of the even and odd 72-bit locations is '0,' which indicates they are cascaded empty, or '1,' which indicates they are occupied. the global full signal indicates to the table con- troller (the host asic) that all entries within a block are occupied and that no more entries can be learned. the m7040n updates the signal after each write or learn command to a data array. the learn command generates a write cycle to the external sram, also using the nfa register as part of the sram address (see sram ad- dressing, page 128). the learn command is supported on a single block containing up to eight devices if the table is configured either as a x72 or a x144. the learn command is not supported for x288-configured ta- bles. learn is a pipelined operation and lasts for two clk cycles, as shown in figure 90, page 121 where tlsz = 00, and figure 91, page 122 and figure 92, page 123 where tlsz = 01 (which as- sume the device performing the learn operation is not the last device in the table and has its lram bit set to '0.' note: the oe_l for the device with the lram bit set goes high for two cycles for each learn (one during the sram write cycle, and one the cycle before). the latency of the sram write cycle from the second cycle of the instruction is shown in table 51, page 123. the sequence of operation is as follows: C cycle 1a : the host asic applies the learn in- struction on the cmd[1:0], using cmdv = 1. the cmd[5:2] field specifies the index of the comparand register pair that will be written in the data array in the 144-bit-configured table. for a learn in a 72-bit-configured table, the even-numbered comparands specified by this index will be written. cmd[8:6] carries the bits that will be driven on sadr[23:21] in the sram write cycle. C cycle 1b : the host asic continues to drive cmdv to '1,' cmd[1:0] to '11,' and cmd[5:2] with the comparand pair index. cmd[6] must be set to '0' if the learn is being performed on a 72-bit-configured table, and to '1' if the learn is being performed on a 144-bit-configured ta- ble. C cycle 2: the host asic drives the cmdv to '0.' at the end of cycle 2, a new instruction can be- gin. the latency of the sram write is the same as the search to the sram read cycle.
121/159 m7040n figure 90. timing diagram of learn: tlsz = 00 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l ssv ssf sadr[23:0] cmd[10:2] phs_ l ai04732 dq a1 a2 tlsz = 00, lram = 1, ldev = 1 learn1 learn2 comp1 1a 1b comp2 x x x x x x x x 1 1 0 0 0 1 0 0 1 0 0 1 0 z
m7040n 122/159 figure 91. timing diagram of learn: tlsz = 01 (except on the last device) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l ssv ssf sadr[23:0] cmd[10:2] phs_ l ai04733 dq a1 tlsz = 01, lram = 0, ldev = 0 learn1 learn2 comp1 1a 1b comp2 x x x x x x x x z z z z z z z z z 0 0 0 0 z a2
123/159 m7040n figure 92. timing diagram of learn on device 7: tlsz = 01 table 51. latency of sram write cycle from second cycle of learn instruction # of devices max table size latency in clk cycles 1 (tlsz = 00) 16k x 72-bit 4 2 C 8 (tlsz = 01) 128k x 72-bit 5 2 C 31 (tlsz = 10) 496k x 72-bit 6 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] ce_l we_l oe_l ssv ssf sadr[23:0] cmd[10:2] phs_ l ai04734 dq tlsz = 01, lram = 1, ldev = 1 learn1 learn2 comp1 1a 1b comp2 x x x x x x x x 1 1 0 0 0 z z 1 1 1 z z 1 z 0 1 z z
m7040n 124/159 depth-cascading the search engine application can depth-cascade the device to various table sizes of different widths (e.g., 72-bit, 144-bit, and 288-bit configurations). the devices perform all the necessary arbitration to decide which device drives the sram bus. the latency of the searches increases as the table size increases while the search rate remains constant. depth-cascading up to eight devices (one block) figure 93, page 125 shows how up to eight devic- es can cascade to form a 512k x 72, 256k x 144, or 128k x 288 bit table. it also shows the intercon- nection between the devices for depth-cascading. each search engine asserts the lho[1] and lho[0] signals to inform downstream devices of its result. the lhi[6:0] signals for a device are con- nected to lho signals of the upstream devices. the host asic must program the tlsz to '01' for each of up to eight devices in a block. only a single device drives the sram bus in any single cycle. depth-cascading up to 31 devices (4 blocks) figure 94, page 126 shows how to cascade up to four blocks. each block contains up to eight m7040ns (except the last block) and the intercon- nection within each is shown in figure 93, page 125. note: the interconnection between blocks for depth-cascading is important. for each search, a block asserts bho[2], bho[1], and bho[0]. the bho[2:0] signals for a block are the signals taken only from the last device in the block. for all other devices within that block, these signals stay open and floating. the host asic must program the ta- ble size (tlsz) field to '10' in each of the devices for cascading up to 31 devices (in up to four blocks). depth-cascading to generate a full signal bit[0] of each of the 72-bit entries is designated as a special bit (1 = occupied; 0 = empty). for each learn or pio write to the data array, each de- vice asserts fulo[1] and fulo[0] if it does not have any empty locations (see figure 95, page 127). each device combines the fulo signals from the devices above it with its own full status to gener- ate a full signal that gives the full status of the table up to the device asserting the full signal. figure 95, page 127 shows the hardware connec- tion diagram for generating the full signal that goes back to the asic. in a depth-cascaded block of up to eight devices, the full signal from the last device should be fed back to the asic control- ler to indicate the fullness of the table. the full signal of the other devices should be left open. note: the learn instruction is supported for only up to eight devices, whereas full cascading is allowed only for one block in tables containing more than eight devices. in tables for which a learn instruction is not going to be used, the bit[0] of each 72-bit entry should always be set to '1.'
125/159 m7040n figure 93. depth-cascading to form a single block sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7040 #0 m7040 #1 m7040 #2 m7040 #3 m7040 #4 m7040 #5 m7040 #6 m7040 #7 lho[0] 654 654 654 654 654 654 654 654 ai04679 ssf, ssv dq[71:0] cmdv cmd[10:0]
m7040n 126/159 figure 94. depth-cascading four blocks sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block of 8 m7040s, block 0 (devices 0-7) block of 8 m7040s, block 1 (devices 8-15) block of 8 m7040s, block 2 (devices 16-23) block of 7 m7040s, block 3 (devices 24-30) ai04684 gnd gnd gnd ssf, ssv cmd[10:0], cmdv dq[71:0]
127/159 m7040n figure 95. full generation in a cascaded table dq[71:0] fulo[1] fulo[0] fulo[0] fulo[1] fulo[0] fulo[0] fulo[0] fulo[0] fulo[0] fulo[1] fulo[1] fulo[1] fuli fuli fuli fuli fuli fuli fuli fuli fuli fuli fuli 3210 3210 3210 3210 3210 3210 3210 3210 m7040 m7040 m7040 m7040 m7040 m7040 m7040 m7040 fulo[0] 654 654 654 654 654 654 654 654 ai04735 full full full full full full full full v ddq v ddq v ddq v ddq v ddq v ddq v ddq
m7040n 128/159 sram addressing table 52 describes the commands used to gener- ate addresses on the sram address bus. the in- dex [15:0] field contains the address of a 72-bit entry that results in a hit in 72-bit-configured quad- rant. it is the address of the 72-bit entry that lies at the 144-bit page, and the 288-bit page boundaries in 144-bit- and 288-bit-configured quadrants, re- spectively. registers, page 22 of this specification, de- scribes the nfa and ssr registers. adr[15:0] contains the address supplied on the dq bus dur- ing pio access to the m7040n. command bits 8, 7, and 6 {cmd[8:6]} are passed from the com- mand to the sram address bus (see command codes and parameters, page 30 for more information). id[4:0] is the id of the device driving the sram bus (see figure 3, page 9 and table 2, page 8 for more information). table 52. generating an sram bus address sram pio access sram read enables read access to off-chip sram that contains associative data. the latency from the issuance of the read instruction to the address appearing on the sram bus is the same as the latency of the search instruction and will depend on the tlsz value parameter pro- grammed in the device configuration register. the latency of the ack from the read instruction is the same as the latency of the search instruc- tion to the sram address plus the hlat pro- grammed in the configuration register. note: sram read is a blocking operation C no new instruction can begin until the ack is returned by the selected device performing the access. sram write enables write access to the off- chip sram containing associative data. the laten- cy from the second cycle of the write instruction to the address appearing on the sram bus is the same as the latency of the search instruction and will depend on the tlsz value parameter pro- grammed in the device configuration register. note: sram write is a pipelined operation C new instruction can begin right after the previous command has ended. sram read with a table of one device sram read enables read access to the off- chip sram containing associative data. the laten- cy from the issuance of the read instruction to the address appearing on the sram bus is the same as the latency of the search instruction and will depend on the tlsz value parameter pro- grammed in the device configuration register. the latency of the ack from the read instruction is the same as the latency of the search instruc- tion to the sram address plus the hlat pro- grammed in the configuration register. the following explains the sram read operation in a table with only one device that has the follow- ing parameters: tlsz = 00, hlat = 000, lram = 1, and ldev = 1. figure 96, page 129 shows the associated timing diagram. for the following description, the selected device refers to the only device in the table because it is the only device to be accessed. the sequence of the operation is as follows: C cycle 1a: the host asic applies the read in- struction on the cmd[1:0], using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram ad- dress. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. during this cycle, the host asic also supplies sadr[23:21] on cmd[8:6] in this cycle. C cycle 1b: the host asic continues to apply the read instruction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram address. command sram operation 23 22 21 [20:16] [15:0] search read c8 c7 c6 id[4:0] index[15:0] learn write c8 c7 c6 id[4:0] nfa[15:0] pio read read c8 c7 c6 id[4:0] adr[15:0] pio write write c8 c7 c6 id[4:0] adr[15:0] indirect access write/read c8 c7 c6 id[4:0] ssr[15:0]
129/159 m7040n C cycle 2: the host asic floats dq[71:0] to a 3- state condition. C cycle 3: the host asic keeps dq[71:0] in a 3- state condition. C cycle 4: theselecteddevicestartstodrive dq[71:0] and drives ack from high-z to low. C cycle 5: the selected device drives the read address on sadr[23:0]; it also drives ack high, ce_l low, and ale_l low. C cycle 6: the selected device drives ce_l high, ale_l high, the sadr bus, and the dq bus in a 3-state condition; it drives ack low. at the end of cycle 6, the selected device floats ack in a 3-state condition, and a new command can begin. figure 96. sram read access for one device cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] ack ssv ssf sadr dq oe_l we_l ce_l phs_ l ai04736 read cmd[10:2] ab address ad dress (dq driven by m7040) hlat = 000, tlsz = 00, lram = 1, ldev = 1 z z 0 1 1 ale_l 1 z 0 0 0 0 1 1 0 1 0 z
m7040n 130/159 sram read with a table of up to eight devices the following explains the sram read operation completed through a table of up to eight devices using the following parameters: tlsz = 01. figure 97, page 131 diagrams a block of eight devices. the following assumes that sram access is suc- cessfully achieved through m7040n device 0. fig- ure 98, page 132 and figure 99, page 133 show timing diagrams for device 0 and device 7, re- spectively. C cycle 1a: the host asic applies the read in- struction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to '10' to select the sram address. the host asic selects the device for which id[4:0] match- es the dq[25:21] lines. during this cycle the host asic also supplies sadr[23:21] on cmd[8:6]. C cycle 1b: the host asic continues to apply the read instruction on the cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram address. C cycle 2: the host asic floats dq[71:0] to a 3- state condition. C cycle 3: the host asic keeps dq[71:0] in a 3- state condition. C cycle 4: theselecteddevicestartstodrive dq[71:0]. C cycle 5: the selected device continues to drive dq[71:0] and drives ack from high-z to low C cycle 6: the selected device drives the read address on sadr[23:0]. it also drives ack high, ce_l low, we_l high, and ale_l low. C cycle 7: the selected device drives ce_l, ale_l, we_l, and the dq bus in a 3-state con- dition. it continues to drive ack low. at the end of cycle 7, the selected device floats ack in 3-state condition and a new command can begin.
131/159 m7040n figure 97. table with eight devices sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7040 #0 m7040 #1 m7040 #2 m7040 #3 m7040 #4 m7040 #5 m7040 #6 m7040 #7 lho[0] 654 654 654 654 654 654 654 654 ai04679 ssf, ssv dq[71:0] cmdv cmd[10:0]
m7040n 132/159 figure 98. sram read through device 0 in a block of eight devices cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 clk2x cmdv cmd[1:0] ack ssv ssf sadr dq oe_l we_l ce_l phs_ l ai04737 read cmd[10:2] ab address ad dress (dq driven by the selected m7040) hlat = 000, tlsz = 01, lram = 0, ldev = 0 z z z z z ale_l z z z z z 0 0 z z 1 z 0 1 0
133/159 m7040n figure 99. sram read timing for device 7 in a block of eight devices cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] ack ssv ssf sadr dq oe_l we_l ce_l phs_ l ai04738 read cmd[10:2] ab ad dress hlat = 000, tlsz = 01, lram = 1, ldev = 1 z 0 1 1 ale_l 1 z z z z z z 1 1 z 1
m7040n 134/159 sram read with a table of up to 31 devices the following explains the sram read operation accomplished through a table of up to 31 devices, using the following parameters: tlsz = 10. the di- agram of such a table is shown in figure 100, page 135. the following assumes that sram access is being accomplished through m7040n device 0 and that device 0 is the selected device. figure 101, page 136 and figure 102, page 137 show the timing di- agrams for device 0 and device 30, respectively. C cycle 1a: the host asic applies the read in- struction to cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to '10,' to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. during this cycle, the host asic also supplies sadr[23:21] on cmd[8:6]. C cycle 1b: the host asic continues to apply the read instruction to cmd[1:0] using cmdv = 1. the dq bus supplies the address, with dq[20:19] set to '10,' to select the sram ad- dress. C cycle 2: the host asic floats dq[71:0] to a 3- state condition. C cycle 3: the host asic keeps dq[71:0] in a 3- state condition. C cycle 4: theselecteddevicestartstodrive dq[71:0]. C cycles 5 to 6: the selected device continues to drive dq[71:0]. C cycle 7: the selected device continues to drive dq[71:0] and drives an sram read cycle. C cycle 8: the selected device drives ack from ztolow. C cycle 9: the selected device drives ack to high. C cycle 10: the selected device drives ack from high to low. at the end of cycle 10, the selected device floats ack in a 3-state condition.
135/159 m7040n figure 100. table of 31 devices made of four blocks sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block of 8 m7040s, block 0 (devices 0-7) block of 8 m7040s, block 1 (devices 8-15) block of 8 m7040s, block 2 (devices 16-23) block of 7 m7040s, block 3 (devices 24-30) ai04684 gnd gnd gnd ssf, ssv cmd[10:0], cmdv dq[71:0]
m7040n 136/159 figure 101. sram read through device 0 in a bank of 31 devices (device 0 timing) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[10:2] ce_l we_l oe_l sadr[23:0] ssv ack ssf phs_ l ale_l ai04739 dq driven by the selected m7040 dq hlat = 010, tlsz = 01, lram = 0, ldev = 0 read address address 00 ab z 0 z 0 z 0 z z z 0 1 z 1 z z z z z z
137/159 m7040n figure 102. sram read through device 0 in a bank of 31 devices (device 30 timing) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[10:2] ce_l we_l oe_l sadr[23:0] ssv ack ssf phs_ l ale_l ai04740 dq hlat = 010, tlsz = 01, lram = 1, ldev = 1 read address 00 ab 1 z 1 z 1 1 1 z 1 z 0 0 0 z
m7040n 138/159 sram write with a table of one device sram write enables write access to the off- chip sram that contains associative data. the la- tency from the second cycle of the write instruc- tion to the address appearing on the sram bus is the same as the latency of the search instruc- tion, and will depend on the tlsz value parameter programmed in the device configuration register. the following explains the sram write opera- tion accomplished with a table of only one device of the following parameters: tlsz = 00, hlat = 000, lram = 1, and ldev = 1. figure 103, page 139 shows the timing diagram. for the following description the selected device refers to the only device in the table as it is the only device that will be accessed. C cycle 1a: the host asic applies the write in- struction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also sup- plies sadr[23:21] on cmd[8:6] in this cycle. note: cmd[2] must be set to '0' for sram write because burst writes into the sram are not supported. C cycle 1b: the host asic continues to apply the write instruction on cmd[1:0], using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram address. note: cmd[2] must be set to '0' for sram write because burst writes into the sram are not supported. C cycle 2: the host asic continues to drive dq[71:0]. the data in this cycle is not used by the m7040n device. C cycle 3: the host asic continues to drive dq[71:0]. the data in this cycle is not used by the m7040n device. at the end of cycle 3, a new command can begin. the write is a pipelined operation. the write cycle appears at the sram bus, however, with the same latency as that of a search instruction, as measured from the second cycle of the write command.
139/159 m7040n figure 103. sram write access for one device cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 clk2x cmdv cmd[1:0] ack ssv ssf sadr dq oe_l we_l ce_l phs_ l ai04741 cmd[10:2] a write b address ad dress hlat = 000, tlsz = 00, lram = 1, ldev = 1 0 1 1 ale_l 1 z 0 0 0 0 0 1 x x
m7040n 140/159 sramwritewithatableofuptoeightdevices the following explains the sram write opera- tion done through a table(s) of up to eight devices with the following parameters (tlsz = 01). the di- agram of such a table is shown in figure 104, page 141. the following assumes that sram access is done through m7040n device 0. figure 105, page 142 and figure 106, page 143 show the timing dia- gram for device 0 and device 7, respectively. C cycle 1a: the host asic applies the write in- struction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also sup- plies sadr[23:21] on cmd[8:6] in this cycle. note: cmd[2] must be set to '0' for sram write because burst writes into the sram are not supported. C cycle 1b: the host asic continues to apply the writeinstructiononcmd[1:0]usingcmdv= 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram ad- dress. note: cmd[2] must be set to '0' for sram write because burst writes into the sram are not supported. C cycle 2: the host asic continues to drive dq[71:0]. the data in this cycle is not used by the m7040n device. C cycle 3: the host asic continues to drive dq[71:0]. the data in this cycle is not used by the m7040n device. at the end of cycle 3, a new command can begin. the write is a pipelined operation. the write cycle appears at the sram bus, however, with the same latency as that of a search instruction, as measured from the second cycle of the write command.
141/159 m7040n figure 104. table with eight devices sram bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bhi[2:0] bho[2] bho[1] bho[0] bho[2] bho[1] bho[0] lho[1] lho[0] lho[0] lho[1] lho[0] lho[0] lho[0] lho[0] lho[0] lho[1] lho[1] lho[1] lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi lhi 3210 3210 3210 3210 3210 3210 3210 3210 m7040 #0 m7040 #1 m7040 #2 m7040 #3 m7040 #4 m7040 #5 m7040 #6 m7040 #7 lho[0] 654 654 654 654 654 654 654 654 ai04679 ssf, ssv dq[71:0] cmdv cmd[10:0]
m7040n 142/159 figure 105. sram write through device 0 in a block of eight devices cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[10:2] ce_l we_l oe_l sadr[23:0] ssv ack ssf phs_ l ale_l ai04742 dq hlat = xxx, tlsz = 01, lram = 0, ldev = 0 write address address 01 ab z 0 z 0 z z z z z z 0 z x x z z z z
143/159 m7040n figure 106. sram write timing for device 7 in a block of eight devices cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[10:2] ce_l we_l oe_l sadr[23:0] ssv ack ssf phs_ l ale_l ai04743 dq hlat = xxx, tlsz = 01, lram = 1, ldev = 1 write address 01 ab 1 z 1 z 1 1 1 z 1 0 1 z 0 0 0 z x x
m7040n 144/159 sramwritewithtable(s)ofupto31devices the following explains the sram write opera- tion done through a table(s) of up to 31 devices with the following parameters (tlsz = 10). the di- agram of such table(s) is shown in figure 107, page 145. the following assumes that sram ac- cess is done through m7040n device 0 C device 0 is the selected device. figure 108, page 146 and figure 109, page 147 show the timing diagram for device 0 and device 30, respectively. C cycle 1a: the host asic applies the write in- struction on cmd[1:0] using cmdv = 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram address. the host asic selects the device for which the id[4:0] matches the dq[25:21] lines. the host asic also sup- plies sadr[23:21] on cmd[8:6] in this cycle. note: cmd[2] must be set to '0' for sram write because burst writes into the sram are not supported. C cycle 1b: the host asic continues to apply the writeinstructiononcmd[1:0]usingcmdv= 1. the dq bus supplies the address with dq[20:19] set to '10' to select the sram ad- dress. note: cmd[2] must be set to '0' for sram write because burst writes into the sram are not supported. C cycle 2: the host asic continues to drive dq[71:0]. the data in this cycle is not used by the m7040n device. C cycle 3: the host asic continues to drive dq[71:0]. the data in this cycle is not used by the m7040n device. at the end of cycle 3, a new command can begin. the write is a pipelined operation. the write cycle appears at the sram bus, however, with the same latency as that of a search instruction, as measured from the second cycle of the write command
145/159 m7040n figure 107. table of 31 devices (four blocks) sram bhi[2] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] bhi[2] bhi[1] bhi[0] bho[2] bho[1] bho[0] block of 8 m7040s, block 0 (devices 0-7) block of 8 m7040s, block 1 (devices 8-15) block of 8 m7040s, block 2 (devices 16-23) block of 7 m7040s, block 3 (devices 24-30) ai04684 gnd gnd gnd ssf, ssv cmd[10:0], cmdv dq[71:0]
m7040n 146/159 figure 108. sram write through device 0 in a bank of 31 devices (device 0 timing) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[10:2] ce_l we_l oe_l sadr[23:0] ssv ack ssf phs_ l ale_l ai04744 dq hlat = xxx, tlsz = 10, lram = 0, ldev = 0 write address address 01 ab z 0 z 0 z z z z z z 0 z x x z z z z
147/159 m7040n figure 109. sram write through device 0 in a bank of 31 devices (device 30 timing) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 7 cycle 6 cycle 8 cycle 10 cycle 9 clk2x cmdv cmd[1:0] cmd[10:2] ce_l we_l oe_l sadr[23:0] ssv ack ssf phs_ l ale_l ai04745 dq hlat = xxx, tlsz = 10, lram = 1, ldev = 1 write address 01 ab 1 z 1 z 1 1 1 z 1 1 z 0 0 0 z x x
m7040n 148/159 jtag (1149.1) testing the m7040n supports the test access port and boundary scan architecture as specified in the ieee jtag standard 1149.1. the pin interface to the chip consists of five signals with the standard definitions: tck, tms, tdi, tdo, and trst_l. table 53 describes the operations that the test ac- cess port controller supports and table 54 de- scribes the tap device id register. note: to disable jtag functionality, connect the tck, tms, and tdi pins to ground, and trst_l to v dd . table 53. supported operations table 54. tap device id register instruction type description sample/preload mandatory sample/preload. loads the values of signals going to and from io pins into the boundary scan shift register to provide a snapshot of the normal functional operation. extest mandatory external test. uses boundary scan values shifted in from tap to test connectivity external to the device. intest optional internal test. allows slow-speed, functional testing of the device using the boundary scan register to provide the i/o values. field range initial value description revision [31:28] 0001 revision number. this is the current device revision number. numbers start from one and increment by one for each revision of the device. part # [27:12] 0000 0000 0000 0100 this is the part number for this device. mfid [11:1] 000_1101_1100 manufacturer id. this field is the same as the manufacturer id used in the tap controller. lsb [0] 1 least significant bit
149/159 m7040n part numbering table 55. ordering information scheme note: 1. where z is the symbol for bga packages and a denotes 1.27mm ball pitch for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m70 40 n C 100 za 1 t device type m70 search engine density 40 = 4.5mb (64k x 72-bit table entries) operating supply voltage n=v dd =1.5vfor C 066 and C 083 speed grades v dd = 1.65v for C 100 speed grade speed C 100 = 100 million searches per second C 083 = 83 million searches per second C 066 = 66 million searches per second package pbga = 388-ball count, 35mm x 35mm (1) , 1.27mm ball pitch temperature range 1 = 0 to 70 c shipping optio n tape & reel packing = t
m7040n 150/159 package mechanical information figure 110. pbga-za C 388-ball plastic ball grid array package outline note: drawing is not to scale. top view pbga-z05 side view detail a a2 a 1.17 ref ddd c 0.56 ref. 30? typ. bottom view d1 e e1 d e b e e pin 1 corner 1 0.20 (4x) detail a d2 e2 b a pin a1 4.00*45? (4x) solder ball (typ) c s c a b fff eee b s s s 1
151/159 m7040n table 56. pbga-za C 388-ball plastic ball grid array package mechanical data note: 1. the terminal b corner must be identified on the top surface by using a corner chamfer, ink, or metallized markings, or other feature of package body or integral heatslug. 2. a distinguished feature is allowable on the bottom surface of the package to identify the terminal ? corner. 3. maximum mounted height is 2.45mm based on a 0.65mm ball pad diameter. solder paste is 0.15mm thickness and 0.65mm in di- ameter. 4. exact shape of each corner is optional. symb mm inches typ min max typ min max a 2.33 2.20 2.46 0.095 0.090 0.100 a2 0.56 0.022 b (1,2) 0.75 0.60 0.90 0.031 0.024 0.037 d (3,4) 35.00 34.80 35.20 1.429 1.420 1.437 d1 31.75 1.296 d2 30.00 1.224 e (3,4) 35.00 34.80 35.20 1.429 1.420 1.437 e 1.27 0.050 e1 31.75 1.296 e2 30.00 1.224 n 388 388 tolerance tolerance ddd 0.15 0.006 eee 0.30 0.012 fff 0.15 0.006
m7040n 152/159 appendix appendix a. descriptions for connection diagram (figure 3, page 9) table 57. connections package ball number signal name signal type package ball number signal name signal type a1 clk_tune[3] (1) note 1 aa26 cmd[2] input a10 dq[43] i/o aa3 v dd 1.5v a11 dq[41] i/o aa4 v ss ground a12 dq[37] i/o ab1 full output-t a13 dq[35] i/o ab2 ack output-t a14 dq[31] i/o ab23 vss ground a15 v ddq (2) 2.5/3.3v ab24 v dd 1.5v a16 dq[25] i/o ab25 cmd[5] input a17 dq[21] i/o ab26 cmd[4] input a18 dq[17] i/o ab3 v dd 1.5v a19 v ddq (2) 2.5/3.3v ab4 v ss ground a2 dq[71] i/o ac1 v ss ground a20 dq[09] i/o ac10 v ss ground a21 dq[05] i/o ac11 v dd 1.5v a22 dq[03] i/o ac12 v dd 1.5v a23 test_fm ground ac13 v dd 1.5v a24 v ddq (2) 2.5/3.3v ac14 v dd 1.5v a25 high_speed input ac15 v dd 1.5v a26 clk_tune[0] (1) note 1 ac16 v dd 1.5v a3 v ddq (2) 2.5/3.3v ac17 v ss ground a4 dq[67] i/o ac18 v ss ground a5 dq[63] i/o ac19 v ss ground a6 v ddq (2) 2.5/3.3v ac2 eot output-t a7 dq[57] i/o ac20 v ss ground a8 dq[53] i/o ac21 v ss ground a9 dq[51] i/o ac22 v ss ground aa1 fulo[1] output-t ac23 v ss ground aa2 v ddq (2) 2.5/3.3v ac24 v dd 1.5v aa23 vss ground ac25 cmd[6] input
153/159 m7040n aa24 v dd 1.5v ac26 v ddq (2) 2.5/3.3v aa25 cmd[3] input ac3 v dd 1.5v ac4 v ss ground ae10 dq[44] i/o ac5 v ss ground ae11 dq[42] i/o ac6 v ss ground ae12 dq[38] i/o ac7 v ss ground ae13 v ddq (2) 2.5/3.3v ac8 v ss ground ae14 dq[32] i/o ac9 v ss ground ae15 dq[28] i/o ad1 rst_l input ae16 dq[26] i/o ad10 dq[46] i/o ae17 v ddq (2) 2.5/3.3v ad11 v dd 1.5v ae18 dq[18] i/o ad12 v dd 1.5v ae19 dq[12] i/o ad13 v dd 1.5v ae2 v ss ground ad14 v dd 1.5v ae20 dq[10] i/o ad15 v dd 1.5v ae21 dq[06] i/o ad16 v dd 1.5v ae22 v ddq (2) 2.5/3.3v ad17 dq[20] i/o ae23 dq[00] i/o ad18 dq[16] i/o ae24 v ddq (2) 2.5/3.3v ad19 nc4 no connect ae25 v ss ground ad2 v ddq (2) 2.5/3.3v ae26 clk_tune[1] (1) note 1 ad20 v dd 1.5v ae3 dq[70] i/o ad21 v dd 1.5v ae4 v ddq (2) 2.5/3.3v ad22 v dd 1.5v ae5 dq[64] i/o ad23 v dd 1.5v ae6 dq[60] i/o ad24 v dd 1.5v ae7 dq[58] i/o ad25 cmd[8] input ae8 dq[54] i/o ad26 cmd[7] input ae9 dq[50] i/o ad3 v dd 1.5v af1 test_co no connect ad4 v dd 1.5v af10 v ddq (2) 2.5/3.3v ad5 v dd 1.5 v af11 dq[40] i/o ad6 v dd 1.5v af12 dq[36] i/o ad7 v dd 1.5v af13 dq[34] i/o ad8 nc3 no connect af14 dq[30] i/o ad9 v ddq (2) 2.5/3.3v af15 v ddq (2) 2.5/3.3v package ball number signal name signal type package ball number signal name signal type
m7040n 154/159 ae1 test ground af16 dq[24] i/o af17 dq[22] i/o b23 test_pb input af18 dq[14] i/o b24 cfg_l input af19 v ddq (2) 2.5/3.3v b25 v ss ground af2 clk_tune[2] (1) note 1 b26 sadr[00] output af20 dq[08] i/o b3 dq[69] i/o af21 dq[04] i/o b4 dq[65] i/o af22 dq[02] i/o b5 dq[61] i/o af23 ssv output-t b6 dq[59] i/o af24 ssf output-t b7 dq[55] i/o af25 cmd[10] input b8 v ddq (2) 2.5/3.3v af26 cmd[9] input b9 dq[47] i/o af3 dq[68] i/o c1 tck input af4 dq[66] i/o c10 v ddq (2) 2.5/3.3v af5 dq[62] i/o c11 v dd 1.5v af6 v ddq (2) 2.5/3.3v c12 v dd 1.5v af7 dq[56] i/o c13 v dd 1.5v af8 dq[52] i/o c14 v dd 1.5v af9 dq[48] i/o c15 v dd 1.5v b1 tdi input c16 v dd 1.5v b10 dq[45] i/o c17 dq[19] i/o b11 dq[39] i/o c18 dq[13] i/o b12 v ddq (2) 2.5/3.3v c19 nc7 no connect b13 dq[33] i/o c2 tms input b14 dq[29] i/o c20 v dd 1.5v b15 dq[27] i/o c21 v dd 1.5v b16 dq[23] i/o c22 v dd 1.5v b17 v ddq (2) 2.5/3.3v c23 v dd 1.5v b18 dq[15] i/o c24 v dd 1.5v b19 dq[11] i/o c25 sadr[01] output b2 v ss ground c26 v ddq (2) 2.5/3.3v b20 dq[07] i/o c3 v dd 1.5v b21 v ddq (2) 2.5/3.3v c4 v dd 1.5v b22 dq[01] i/o c5 v dd 1.5v package ball number signal name signal type package ball number signal name signal type
155/159 m7040n c6 v dd 1.5v e24 v dd 1.5v c7 v dd 1.5v e25 sadr[05] output c8 nc8 no connect e26 sadr[04] output c9 dq[49] i/o e3 v dd 1.5v d1 trst_l input e4 v ss ground d10 vss ground f1 id[1] input d11 v dd 1.5v f2 id[2] input d12 v dd 1.5v f23 v ss ground d13 v dd 1.5v f24 v dd 1.5v d14 v dd 1.5v f25 sadr[06] output d15 v dd 1.5v f26 v ddq (2) 2.5/3.3v d16 v dd 1.5v f3 v dd 1.5v d17 v ss ground f4 v ss ground d18 v ss ground g1 id[3] input d19 v ss ground g2 id[4] input d2 tdo output-t g23 v ss ground d20 v ss ground g24 v dd 1.5v d21 v ss ground g25 sadr[08] output d22 v ss ground g26 sadr[07] output d23 v ss ground g3 v dd 1.5v d24 v dd 1.5v g4 v ss ground d25 sadr[03] output h1 lhi[0] input d26 sadr[02] output h2 lhi[1] input d3 v dd 1.5v h23 v ss ground d4 v ss ground h24 nc6 no connect d5 v ss ground h25 v ddq (2) 2.5/3.3v d6 v ss ground h26 sadr[09] output d7 v ss ground h3 nc1 no connect d8 v ss ground h4 v ss ground d9 v ss ground j1 lhi[2] input e1 id[0] input j2 lhi[3] input e2 v ddq (2) 2.5/3.3v j23 v ss ground e23 v ss ground j24 sadr[11] output j25 sadr[12] output m2 bhi[0] input package ball number signal name signal type package ball number signal name signal type
m7040n 156/159 j26 sadr[10] output m23 v dd 1.5v j3 v ddq (2) 2.5/3.3v m24 v dd 1.5v j4 v ss ground m25 v ddq (2) 2.5/3.3v k1 lhi[6] input m26 sadr[17] output k2 lhi[4] input m3 v dd 1.5v k23 v ss ground m4 v dd 1.5v k24 sadr[13] output n1 bhi[1] input k25 v ddq (2) 2.5/3.3v n11 v ss ground k26 sadr[14] output n12 v ss ground k3 lhi[5] input n13 v ss ground k4 v ss ground n14 v ss ground l1 lho[0] output-t n15 v ss ground l11 v ss ground n16 v ss ground l12 v ss ground n2 bhi[2] input l13 v ss ground n23 v dd 1.5v l14 v ss ground n24 v dd 1.5v l15 v ss ground n25 sadr[19] output l16 v ss ground n26 sadr[18] output l2 lho[1] output-t n3 v dd 1.5v l23 v dd 1.5v n4 v dd 1.5v l24 v dd 1.5v p1 bho[0] output-t l25 sadr[15] output p11 v ss ground l26 sadr[16] output p12 v ss ground l3 v dd 1.5v p13 v ss ground l4 v dd 1.5v p14 v ss ground m1 v ddq (2) 2.5/3.3v p15 v ss ground m11 v ss ground p16 v ss ground m12 v ss ground p2 multi_hit output-t m13 v ss ground p23 v dd 1.5v m14 v ss ground p24 v dd 1.5v m15 v ss ground p25 sadr[21] output m16 v ss ground p26 sadr[20] output p3 v dd 1.5v u24 oe_l output-t p4 v dd 1.5v u25 phs_l input package ball number signal name signal type package ball number signal name signal type
157/159 m7040n note: 1. clk_tune[3:0] should be programmed to 100%. 2. all v ddq pins should be set to 2.5 or 3.3v. r1 v ddq (2) 2.5/3.3v u26 clk1x/clk2x input r11 v ss ground u3 fuli[1] input r12 v ss ground u4 v ss ground r13 v ss ground v1 fuli[2] input r14 v ss ground v2 fuli[3] input r15 v ss ground v23 v ss ground r16 v ss ground v24 ce_l output-t r2 bho[1] output-t v25 v ddq (2) 2.5/3.3v r23 v dd 1.5v v26 we_l output-t r24 v dd 1.5v v3 fuli[4] input r25 sadr[22] output v4 v ss ground r26 v ddq (2) 2.5/3.3v w1 v ddq (2) 2.5/3.3v r3 v dd 1.5v w2 fuli[5] input r4 v dd 1.5v w23 v ss ground t1 bho[2] output-t w24 nc5 no connect t11 v ss ground w25 cmdv input t12 v ss ground w26 ale_l output-t t13 v ss ground w3 nc2 no connect t14 v ss ground w4 v ss ground t15 v ss ground y1 fuli[6] input t16 v ss ground y2 fulo[0] output-t t2 v ss ground y23 v ss ground t23 v dd 1.5v y24 v dd 1.5v t24 v dd 1.5v y25 cmd[1] input t25 clk_mode input y26 cmd[0] input t26 sadr[23] output y3 v dd 1.5v t3 v dd 1.5v y4 v ss ground t4 v dd 1.5v u1 fuli[0] input u2 v ddq (2) 2.5/3.3v u23 v ss ground package ball number signal name signal type package ball number signal name signal type
m7040n 158/159 revision history table 58. document revision history date revision details april 2001 first issue 07/23/01 routine maintenance (based on recent data sheet review findings) 10/16/01 addition of 1.8v data 10/29/01 document promoted to ?reliminary data; v ddq corrected (table 4) 04/03/02 updates per engineering (figure 3); (table 1, 2, 3, 4, 6, 8, 55) 4/19/02 improve mechanical, connection drawings (figures 3, 110); change register overview (table 9) 05/10/02 modify timing diagrams (figure 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 91, 99, 103)
159/159 m7040n information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

▲Up To Search▲

Price & Availability of M7040N-083ZA1T

	To Download M7040N-083ZA1T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .